- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245657 > W25Q64BVSSIG (WINBOND ELECTRONICS CORP) 8M X 8 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數(shù)資料
| 型號： | W25Q64BVSSIG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.208 INCH, GREEN, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 25/61頁 |
| 文件大小： | 1726K |
| 代理商： | W25Q64BVSSIG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當(dāng)前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁
W25Q64BV
Publication Release Date: July 08, 2010
- 31 -
Revision E
11.2.14 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the four dummy clocks
are not required, which further reduces the instruction overhead allowing even faster random access for
code execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal
Word Read Quad I/O Instruction. To ensure optimum performance the High Performance Mode
(HPM)instruction (A3h) must be executed once, prior to the Octal Word Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 14a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits (M7-0) equals “Ax” hex, then the next Octal Word Read Quad I/O
instruction (after /CS is raised and then lowered) does not require the E3h instruction code, as shown in
figure 14b. This reduces the instruction sequence by eight clocks and allows the Read address to be
immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits (M7-0) are any value
other than “Ax” hex, the next instruction (after /CS is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation. A “Continuous Read Mode” Reset instruction can be
used to reset (M7-0) before issuing normal instructions (See 11.2.29 for detailed descriptions).
Figure 14a. Octal Word Read Quad I/O Instruction Sequence (M7-0 = 0xh or NOT Axh)
Instruction (E3h)
Byte 1
Byte 2
Byte 3
40
4
0
40
51
5
1
51
62
6
2
62
73
7
3
73
40
51
62
73
Byte 4
Instruction (E3h)
Byte 1
Byte 2
Byte 3
40
4
0
40
51
5
1
51
62
6
2
62
73
7
3
73
40
51
62
73
Byte 4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WE128K8-250CCA | EEPROM 5V MODULE, CDIP32 |
| W25Q16CVTCAG | 16M X 1 SPI BUS SERIAL EEPROM, PBGA24 |
| WF2M32S-100HM | 8M X 8 FLASH 5V PROM MODULE, 100 ns, CHIP66 |
| WF2M32S-100HC | 8M X 8 FLASH 5V PROM MODULE, 100 ns, CHIP66 |
| WF2M32S-120GTC | 8M X 8 FLASH 5V PROM MODULE, 120 ns, CQFP68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W25Q64BVSSIGTR | 制造商:Winbond Electronics Corp 功能描述:SPIFLASH, 64M-BIT, 4KB UNIFORM |
| W25Q64BVSSIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64BVZEIG | 功能描述:IC SPI FLASH 64MBIT 8WSON RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:SpiFlash® 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| W25Q64BVZEIP | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
| W25Q64CV | 制造商:WINBOND 制造商全稱:Winbond 功能描述:3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。