APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD
677
(3/5)
Page
Description
Classification
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS H0 AND H1
p. 258
Partial change of description of RMC1 and NRZB1 bits in and addition of Caution to Figure 9-7
Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
(c)
p. 261
Change of (c) Operation when CMP0n = 00H in Figure 9-10 Timing of Interval Timer/Square-
Wave Output Operation
(a)
p. 268
Partial change of description of RMC1 and NRZB1 bits in 9.4.3 (2) Carrier output control
(c)
CHAPTER 11 WATCHDOG TIMER
pp. 285, 286
Change of Caution 5 in 11.4.1 Controlling operation of watchdog timer and Caution 2 in Table
11-3 Setting of Overflow Time of Watchdog Timer and Table 11-4 Setting Window Open
Period of Watchdog Timer
(c)
CHAPTER 12 CLOCK OUTPUT CONTROLLER
p. 290
Change of Figure 12-2 Format of Clock Output Selection Register (CKS)
(a)
CHAPTER 13 A/D CONVERTER
p. 302
Change of setting of digital input and output in Table 13-3 Setting Functions of ANI0/P20 to
ANI7/P27 Pins
(a)
CHAPTER 14 SERIAL INTERFACE UART0
p. 314
Change of maximum transfer rate in 14.1 Functions of Serial Interface UART0
(b)
p. 332
Addition of setting data when target baud rate is 312500 bps and 625000 bps to Table 14-5 Set
Data of Baud Rate Generator
(b), (c)
CHAPTER 15 SERIAL INTERFACE UART6
p. 335
Change of maximum transfer rate in 15.1 Functions of Serial Interface UART6
(b)
p. 347
Change of output clock selection range and Remark 2 in Figure 15-9 Format of Baud Rate
Generator Control Register 6 (BRGC6)
(b)
p. 366
Partial change of description in 15.4.3 (2) Generation of serial clock
(b)
p. 368
Addition of data to be set where target baud rate is 625000 bps to and change of Remark in Table
15-5 Set Data of Baud Rate Generator
(b), (c)
p. 370
Addition of error if division ratio (k) is 4 to Table 15-6 Maximum/Minimum Permissible Baud
Rate Error
(b)
CHAPTER 16 SERIAL INTERFACE CSI10 AND CSI11
p. 378
Change of Figure 16-5 Format of Serial Clock Selection Register 10 (CSIC10)
(b)
p. 379
Change of Figure 16-6 Format of Serial Clock Selection Register 11 (CSIC11)
(b)
CHAPTER 17 SERIAL INTERFACE IIC0
p. 397
Addition of Port register 6 to Table 17-1 Configuration of Serial Interface IIC0
(c)
p. 400
Addition of Port register 6 to 17.3 Registers to Control Serial Interface IIC0
(c)
p. 408
Partial change of condition in which STCEN bit is cleared in Figure 17-7 Format of IIC Flag
Register 0 (IICF0)
(a)
p. 413
Addition of 17.3 (8) Port register 6 (P6)
(c)
p. 430
Addition of descriptions (1) Master operation in single master system, (2) Master operation in
multimaster system, and (3) Slave operation to 17.5.16 Communication operations
(c)
p. 431
Partial change of Figure 17-24 Master Operation in Single-Master System
(c)
p. 436
Partial change of Figure 17-26 Slave Operation Flowchart (1)
(c)
Remark
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents