
User’s Manual U17473EJ2V0UD
9
CONTENTS
CHAPTER 1 OUTLINE......................................................................................................................................................................17
1.1 Features ........................................................................................................................................ 17
1.2 Applications.................................................................................................................................. 18
1.3 Ordering Information ................................................................................................................... 18
1.4 Pin Configuration (Top View)...................................................................................................... 19
1.5 Configuration................................................................................................................................ 22
1.6 78K0/Lx2 Series Lineup............................................................................................................... 23
1.7 Block Diagram .............................................................................................................................. 25
1.8 Outline of Functions .................................................................................................................... 26
CHAPTER 2 PIN FUNCTIONS.......................................................................................................................................................29
2.1 Pin Function List .......................................................................................................................... 29
2.2 Description of Pin Functions ...................................................................................................... 33
2.2.1 P00 to P06 (port 0)...........................................................................................................................33
2.2.2 P10 to P17 (port 1)...........................................................................................................................34
2.2.3 P20 to P27 (port 2)...........................................................................................................................35
2.2.4 P30 to P33 (port 3)...........................................................................................................................35
2.2.5 P60, P61 (port 6) .............................................................................................................................36
2.2.6 P70 to P77 (port 7)...........................................................................................................................36
2.2.7 P120 to P124 (port 12).....................................................................................................................36
2.2.8 AVREF ...............................................................................................................................................37
2.2.9 AVSS.................................................................................................................................................37
2.2.10 S0 to S39 .......................................................................................................................................37
2.2.11 COM0 to COM3 .............................................................................................................................37
2.2.12 LVDD ...............................................................................................................................................37
2.2.13 LVSS ...............................................................................................................................................37
2.2.14 VLC0 to VLC2 ....................................................................................................................................38
2.2.15 CAPH, CAPL .................................................................................................................................38
2.2.16 RESET...........................................................................................................................................38
2.2.17 REGC ............................................................................................................................................38
2.2.18 VDD .................................................................................................................................................38
2.2.19 VSS .................................................................................................................................................38
2.2.20 FLMD0 ...........................................................................................................................................38
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 39
CHAPTER 3 CPU ARCHITECTURE............................................................................................................................................43
3.1 Memory Space .............................................................................................................................. 43
3.1.1 Internal program memory space ......................................................................................................50
3.1.2 Memory bank (
μPD78F0396, 78F0397, and 78F0397D only) .........................................................51
3.1.3 Internal data memory space ............................................................................................................51
3.1.4 Special function register (SFR) area ................................................................................................52
3.1.5 Data memory addressing.................................................................................................................52
3.2 Processor Registers .................................................................................................................... 58
3.2.1 Control registers...............................................................................................................................58