![](http://datasheet.mmic.net.cn/Renesas-Electronics-America/UPD78F0394GC-8EA-A_datasheet_99854/UPD78F0394GC-8EA-A_678.png)
APPENDIX C REVISION HISTORY
User’s Manual U17473EJ2V0UD
676
(2/5)
Page
Description
Classification
CHAPTER 3 CPU ARCHITECTURE
p. 74
Modification of [Description example] in 3.4.4 Short direct addressing
(c)
p. 76
Addition to description in 3.4.6 Register indirect addressing
(c)
p. 77
Addition to description in 3.4.7 Based addressing
(c)
p. 78
Addition to description in 3.4.8 Based indexed addressing
(c)
CHAPTER 4 MEMORY BANK SELECT FUNCTION (
μPD78F0396, 78F0397, AND 78F0397D ONLY)
pp. 80 to 89
Addition of chapter
(c)
CHAPTER 5 PORT FUNCTIONS
p. 104
Change of setting of digital input and output in Table 5-4 Setting Functions of P20/ANI0 to
P27/ANI7 Pins
(a)
p. 104
Addition of Caution to 5.2.3 Port 2
(c)
p. 112
Addition of Note to Figure 5-21 Format of Port Register
(c)
p. 117
Change of setting of digital input and output in Table 5-6 Setting Functions of ANI0/P20 to
ANI7/P27 Pins
(a)
p. 118
Addition of 5.6 Cautions on 1-bit Manipulation Instruction for Port Register n (Pn)
(c)
CHAPTER 6 CLOCK GENERATOR
p. 121
Addition of OR circuit to Figure 6-1 Block Diagram of Clock Generator
(a)
p. 123
Change of Cautions 2 and 3 (description concerning stopping time of supplying CPU clock) in
Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)
(b)
p. 131
Addition of description of external clock input to 6.4.1 X1 oscillator and 6.4.2 XT1 oscillator
(c)
pp. 136, 137
Change of Figure 6-12 Clock Generator Operation When Power Supply Voltage Is Turned On
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
(b)
p. 137
Addition of Figure 6-13 Clock Generator Operation When Power Supply Voltage Is Turned
On (When 2.7 V/1.59 V POC Mode Is Set (Option Byte: POCMODE = 1))
(b)
pp. 139, 140
Partial change (CPU clock supply stop time when AMPH = 1) of Note in 6.6.1 (1) <1> Setting
frequency (OSCCTL register) and 6.6.1 (2) <1> Setting frequency (OSCCTL register)
(b)
p. 147
Addition of Remark to Figure 6-14 CPU Clock Status Transition Diagram (When 1.59 V POC
Mode Is Set (Option Byte: POCMODE = 0))
(c)
p. 152
Change of CPU clock supply stop time when AMPH = 1 in Table 6-6 Changing CPU Clock
(b)
p. 153
Change of Remark 2 in Table 6-7 Time Required for Switchover of CPU Clock and Main
System Clock Cycle Division Factor
(a)
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
pp. 156 to 232
Revision of chapter
(c)
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
p. 239
Change of Caution 3 in Figure 8-7 Format of 8-Bit Timer Mode Control Register 50 (TMC50)
and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51 (TMC51)
(c)
p. 243
Change of set value of TMC5n in Setting <1> in 8.4.2 Operation as external event counter
(a)
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS H0 AND H1
p. 253
Change of Caution in Figure 9-3 Format of 8-Bit Timer H Compare Register 0n (CMP0n)
(c)
p. 253
Partial addition of description to 9.2 (2) 8-bit timer H compare register 1n (CMP1n)
(c)
pp. 256, 257
Change of Caution 1 of Figure 9-5 Format of 8-Bit Timer H Mode Register 0 (TMHMD0) and
Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
(c)
Remark
“Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents