參數(shù)資料
型號(hào)： TMC2376
廠(chǎng)商： Fairchild Semiconductor Corporation
英文描述： PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器)
中文描述： PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器）
文件頁(yè)數(shù)： 7/48頁(yè)
文件大?。?/td> 233K
代理商： TMC2376
TMC2376
PRODUCT SPECIFICATION
7
P
Frame Buffer Port
D15-0
100-97,
94-91, 88-81
118-107
TTL input/
output
TTL output
Data port, frame store memory.
16-bit data bus for 16M SDRAM.
A11-0
Address port, frame store memory.
12-bit address bus for 16M
SDRAM.
Row address strobe.
RAS output for 16M SDRAM frame store
memory.
Column address strobe.
CAS output for 16M SDRAM frame store
memory.
Write enable.
WE output for 16M SDRAM frame store memory.
Data Qualify.
Qualify data for 16M SDRAM frame store read/write
operations. State is set by the memory access mode:
DQM = L, enables memory outputs for read operations and
exposes memory inputs for write operations.
DQM = H, disables memory outputs and masks memory inputs
RAS
78
TTL output
CAS
79
TTL output
WE
DQM
76
75
TTL output
TTL output
CS
77
TTL output
SDRAM chip select.
CS output for 16M SDRAM frame store
memory.
Frame store clock input.
Clock input to be routed to FSCK_OUT
selected if FSCK_SEL = L.
FSCK_IN
127
TTL
compatible
input
TTL input
FSCKXSEL\
125
Frame store clock select.
Selects either internal or external clock
for 16M SDRAM frame store memory. If FSCKXSEL\ = H, the internal
clock synthesized from CKNTSC is selected. With FSCKXSEL\ = L,
the FSCK_IN input is selected.
Frame store clock output
. FSCK_OUT for 16M SDRAM frame
store memory.
FSCK_OUT
126
TTL output
Serial Port
SA10/7
31
TTL input
Serial address length select.
Selects the length of the serial
address:
SA10/7 = L: 10-bits
SA10/7 = H: 7-bits
Serial data address bit 0.
. Selects the serial bus address
SA0 = L: 0x6A, Ox276
SA0 = H: 0x4A, Ox224
Serial data.
Data line of the serial port.
Serial clock.
Clock line of the serial port.
SA0
32
TTL input
SDA
SCL
Power and Ground
VDDAD
VDDPA
30
29
TTL input
TTL input
42, 46, 47, 54
68
+5.0 V
+5.0 V
A/D converter Power.
ADCK Phase-locked loop Power
. Filtered
+5 volt power for ADCK
phase locked loop.
Digital Power.
3.3 volt power for memory interface.
VDD3
90, 95, 106
+3.3 V
Pin Descriptions
(continued)
Pin Name
Pin
Number
128-pin
MQFP
Type/Value
Pin Function Description
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