參數(shù)資料
型號： TMC2376
廠商： Fairchild Semiconductor Corporation
英文描述： PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器)
中文描述： PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器）
文件頁數(shù)： 5/48頁
文件大小： 233K
代理商： TMC2376
TMC2376
PRODUCT SPECIFICATION
5
P
Pin Descriptions
Pin Name
Clocks
CKNTSC
Pin
Number
128-pin
MQFP
Type/Value
Pin Function Description
1
TTL
compatible
input
Reference Clock Input, NTSC.
Input from 14.31818 MHz external
oscillator; or one pin of a crystal connected between CKNTSC and
XTALNTSC. NTSC subcarrier frequency is derived from this 4x
clock. CKNTSC must be connected (see Table 4. 4x Clock
Connections)
NTSC Crystal Return.
If a crystal is used, connect one pin to
CKNTSC, the other to XTALNTSC.
Reference Clock, PAL.
Input from 17.734475 MHz external
oscillator; or one pin of a crystal connected between CKPAL and
XTALPAL. PAL subcarrier frequency is derived from this 4x clock.
PAL Crystal Return.
If a crystal is used, connect one pin to CKPAL,
the other to XTALPAL.
VGA Horizontal Sync Input.
Active HIGH or active LOW polarity is
sensed.
VGA Vertical Sync Input.
Active HIGH or active LOW polarity is
sensed.
XTALNTSC
2
TTL output
CKPAL
3
TTL
compatible
input
TTL output
XTALPAL
4
HS
63
TTL input
VS
62
TTL input
Global Controls
FLP_RST
36
TTL input
Field, Line and Pixel Reset.
Resets video encoder engine to the
start location on the outgoing frame. Used for genlock.
Reset.
Resets internal state machines and initializes default register
values.
RESET
37
TTL input
A/D Converter Interface
R, G, B
45, 48, 53
700/1000
mV pp
Analog red, blue and green inputs.
AC coupled RGB video input
signals. Nominal voltage range is 0.7 Volt peak-to-peak. Inputs are
clamped to ground when HS_IN is active.
750/1050 mV
A/D Converter Top Reference Voltage Input.
Input to voltage
follower that supplies current to A/D converter reference resistors.
Range is 0.5 - 2.0 volts.
750/1050 mV
A/D Converter Top Reference Voltage Output.
Voltage follower
connection to top of A/D converter reference resistors.
TTL
compatible
input
TTL input
ADXCK select.
Selects the ADCK source:
ADXCKSEL\ = L:
external clock applied to the ADXCK pin.
ADXCKSEL\ = H:
internal phase-locked loop.
TTL output
ADCK divided by N.
ADCK divided by N for connection to external
phase-locked loop controller.
TTL output
Clamp out.
Clamp output signal. CLAMPO = H, when the internal
clamp is active during the horizontal sync period, HS_IN.
VT
51
VTOUT
50
ADXCK
67
A/D converter clock.
Analog-to-digital converter external clock input
if ADXCKSEL = H.
ADXCKSEL\
66
ADCK/N
65
CLAMP
55
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