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參數(shù)資料
| 型號(hào)： | TMC2376 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器) |
| 中文描述： | PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器） |
| 文件頁數(shù)： | 24/48頁 |
| 文件大?。?/td> | 233K |
| 代理商： | TMC2376 |
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TMC2376
PRODUCT SPECIFICATION
24
P
Timing and Control
Timing of the Encoder Engine is Synchronized by the
Encoder Timing and Control Block. Frame store clock,
FS_CK is derived from the CKNTSC clock by the FSCK
phase locked loop.
Either of two 4x subcarrier clocks can be selected to syn-
chronize the Encoder Engine. Frequencies are:
CKNTSC: 14.31818 MHz for NTSC.
CKPAL: 17.734475 MHz for PAL.
A clock signal must always be applied to the 4x NTSC clock
input, CKNTSC. Depending upon the outgoing TV standard
requirements, one of three possible clock combinations can
be selected as depicted in Table 6.
Table 6. 4x Clock Connections
Horizontal Scaler
Pixels extracted from the external frame store memory
are passed to the Horizontal Scaler by the Frame Store
Controller.
Horizontal scale factor is set by programming the HSC regis-
ters (register no.’s 0x24 and 0x25). HSC is the Horizontal
scaling coefficient, m that determines the horizontal scaling
factor:
HSF = (1 + m/64)
With a range: 0
≤
m
≤
63; 1
≤
HSF
≤
1 + 63/64
Digital Video Encoder
For CVBS and Y/C outputs, pixels from the Horizontal
Scaler are routed to the Video Encoder. NTSC (SMPTE
170M) and PAL (CCIR 624) standards are preprogrammed
into the Video Encoder to preset horizontal and vertical tim-
ing, subcarrier frequency, and chrominance phase.
Setting the Command Register DACFMT1-0 bits to 00
selects CVBS and Y/C outputs. Mode register bit 1 PAL/
NTSC selects either PAL or NTSC timing.
Mode Register bit, CBPF inserts a 18% (0.64 MHz for
NTSC; 0.8 MHz for PAL) fSC bandpass filter centered at
fSC following the chroma modulator.
Mode Register bit, LUMNTCH insert a luminance notch fil-
ter in the Y channel prior to the CVBS summer and the Y
output.
Mode Register Extended bit, OCS set the gain of the U and
V channels prior to the chroma modulator.
YUV/RGB Matrix
For RGB outputs, pixels from the Horizontal Scaler are
routed to the YUV/RGB matrix. Matrix coefficients are pro-
grammed by setting the DACFMT1-0 bits in the Mode regis-
ter. For a YUV output, the DACFMT1-0 bits can be set to
bypass the YUV/RGB matrix.
Digital-to-Analog Converters
Three 9-bit D/A converters accept data from either the video
encoder or the YUV-to-RGB transcoder. Each output is a
current source connected to the analog V
DDDA
supply. Cur-
rent is injected into external resistor to develop the output
voltage. Typically the DC load is 37.5
formed from two
75
resistors and a low pass filter. A 75
load may be
selected to minimize power dissipation.
Peak output current of the D/A converters is established by
VREF and an external resistor connected between RREF and
ground. Peak current is six times the current through the ref-
erence resistor.
An internal 1.235 volt reference is buffered from V
REF
by a
resistor, to enable V
REF
to be overridden by an external volt-
age. Output current may be calibrated by resistor selection or
by setting a potentiometer attached to R
REF
.
For 1.3 volt video, with a 37.5
load, the correct value of
R
REF
is 392
. With a 75
load, the correct value of R
REF
is
768
. See applications circuits.
To minimize DAC noise, a bypass capacitor must be con-
nected from C
BYPR
to an adjacent V
DDDA
pin.
Power may be conserved by disabling the power supplied to
unused D/A converters. Mode Register bit CVBSOFF con-
trols CVBS D/A converter power. Mode Register bit YCOFF
controls Y/C D/A converter.
Serial Control Port (R-Bus)
All TMC2376 register access is via a 2-wire serial control
interface. Either 7 or 10-bit addressing may be used with two
addresses available for each type of addressing scheme.
(see Table 7)
Two signals comprise the bus: clock (SCL) and bi-direc-
tional data (SDA). The TMC2376 acts as a slave for receiv-
ing and transmitting data over the serial interface.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
TV Standard
NTSC and PAL
NTSC only
PAL only
CKNTSC
CKPAL
N/A
Connect to CKPAL
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