參數(shù)資料
型號： TMC2376
廠商： Fairchild Semiconductor Corporation
英文描述： PC-to-TV Video Standards Converter(PC到TV視頻標準變換器)
中文描述： PC到電視視頻標準轉(zhuǎn)換器（電腦到電視視頻標準變換器）
文件頁數(shù)： 31/48頁
文件大?。?/td> 233K
代理商： TMC2376
TMC2376
PRODUCT SPECIFICATION
31
P
Switching Characteristics
Notes:
1. Values shown in Typ column are typical for VDD5 = VDDA = +5V, VDD3 = +3.3V and TA = 25_C.
2. TV subcarrier acceptance band is
±
300 Hz.
Parameter
Clocks
fXTOL
tPWH
tPWL
Incoming Syncs
fH
fV
NH
tPWHS
tVS-HS
Video Output
tDOV
Conditions
Min
Typ1
Max
Unit
Reference Clock Frequency Tolerance
Reference Clock Pulse Width, HIGH
Reference Clock Pulse Width, LOW
50
40
40
50
1
ppm
ns
ns
HS_IN frequency
VS_IN frequency
Number of lines per frame
HS_IN Pulsewidth
VS_IN to HS_IN Delay
25
50
400
1
0
75
90
850
KHz
Hz
μ
s
ns
Analog Output Delay (4fSC clock to
Video Out)
D/A Output Current Risetime
(10% to 90%)
D/A Output Current Falltime
(90% to 10%)
D/A to D/A Skew
SDRAM Frame Buffer Interface
tFCKL
FS_CK out pulse width, LOW
tFCKH
FS_CK out pulse width, HIGH
tFSCO
FS_CK out to CS, RAS, CAS, WE DQM
out delay
tFDSU
FS_CK out to data in setup time
tFDHO
FS_CK out to data in hold time
tFDO
FS_CK out to data out delay
tFAO
FS_CK out to address out delay
Serial Microprocessor Interface
tDAL
SCL Pulse Width, LOW
tDAH
SCL Pulse Width, HIGH
tSTAH
SDA Start Hold Time
tSTASU
SCL to SDA Setup Time (Stop)
tSTOSU
SCL to SDA Setup Time (Start)
tBUFF
SDA Stop Hold Time Setup
tDSU
SDA to SCL Data Setup Time
tDHO
SDA to SCL Data Hold Time
30
ns
tR
10
ns
tF
10
ns
SKEW
-3
0
3
ns
5.0
5.0
2.0
ns
ns
ns
3.0
3.0
2.0
2.0
ns
ns
ns
ns
1.3
0.6
0.6
0.6
0.6
1.3
300
300
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
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