參數(shù)資料
型號(hào)： TMC2376
廠商： Fairchild Semiconductor Corporation
英文描述： PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器)
中文描述： PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器）
文件頁數(shù)： 1/48頁
文件大小： 233K
代理商： TMC2376
P
T MC2376
PC-to-T V Video S tandards Converter
www.fairchildsemi.com
PRELIMINARY INFORMATION
describes products that are not in full production at the time of printing. Specifications are based
on design goals and limited characterization. The may change without notice. Contact Fairchild for current information.
V
T
R
7-0
G
7-0
B
7-0
Timing and
Control
RGB/YC
B
C
R
Matrix
Vertical
Scaler
Flicker
Filter
YC
B
C
R
/RGB
Matrix
Video
Encoder
FLP_RST
Horizontal
Scaller
8-bit
A/D
8-bit
A/D
8-bit
A/D
9-bit
D/A
9-bit
D/A
9-bit
D/A
Frame Store
Controller
XTALNTSC
XTALPAL
C
R
A
1
R
W
F
D
C
F
F
D
1
R
R
V
R
C
B
R
G
B
Y/R/V
CVBS/G/Y
C/B/U
CSYNC
ADXCK
ADXCKSEL\
ADCK/N
CKNTSC
CKPAL
HS
VS
XAD_SEL\
CLAMP
2366-01
Serial Bus
Interface
S
S
0
S
S
Features
Programmable to VESA and Industry Standard timing
modes.
Frame rate Conversion
Programmable 2D scaling
Frame-store memory controller
Accepts 640x480 , 800x600, 1024x768 VGA, Mac
Multiple output standards: NTSC, NTSC-EIA,
PAL-B/G/H/I, SCART, Y/C, CVBS, RGB, YUV formats
Pan and Zoom
3-Line Flicker filter
I
2
C compatible port controls
Synclock
8-bit A/D converters
24-bit RGB input port
9-bit output D/A converters
Applications
PC video inputs for TVs or interlaced monitors
TV out for PCs, VGA or graphics cards
Internet appliances, net browsers
Video Kiosks
See use restrictions on backpage.
Architectural Block Diagram
Description
A range of VGA formats/refresh rates can be converted to
NTSC and PAL standards compliant with SMPTE-170M
and CCIR-624 standards. Within the TMC2376 are
capture and encoder engines separated by the frame buffer
memory controller. Required external components are
minimal: 16M SDRAM memory, clocks and passive parts.
RGB video inputs are converted to the YUV422 format.
Vertical scaling and flicker filtering are implemented at the
VGA frame rate ahead of the frame store interface.
Frame rate conversion is implemented with by a Frame Store
Controller that interfaces with an external SDRAM frame
store memory.
YUV422 data is recovered from the memory at the outgoing
frame rate. Data is scaled prior to the digital video encoder
which generates Y/C and CVBS outputs. For RGB outputs,
the encoder may be bypassed via a YUV to RGB transcoder
for SCART compatible video.
Setup is via an I
2
C compatible serial port. Power is derived
from +3.3V and +5V supplies. Package is a 128-lead Metric
Quad Flat Pack (MQFP).
Rev. 0.9.4
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