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參數(shù)資料
| 型號： | TMC2376 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PC-to-TV Video Standards Converter(PC到TV視頻標準變換器) |
| 中文描述： | PC到電視視頻標準轉(zhuǎn)換器（電腦到電視視頻標準變換器） |
| 文件頁數(shù)： | 22/48頁 |
| 文件大小： | 233K |
| 代理商： | TMC2376 |
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TMC2376
PRODUCT SPECIFICATION
22
P
Phase Locked Loop
All SDRAM access is synchronized to the selected 4f
SC
clock derived from the CKNTSC clock input. The 4f
SC
clock
is divided by two, then depending upon the outgoing video
standard selection, either NTSC or PAL, multiplied x9 or
x11 by the Frame Store Controller Phase Locked Loop to
create the 80 MHz SDRAM clock, FSCK
FSCKXSEL\ selects either internal clock, FSCK or external
input FSCK_IN which should have a frequency of 80 MHz
to accomodate high resolution images (1024x768) refreshed
at high rates (75 Hz) converted to the PAL format (17.73
MHz 4f
SC
clock).
Input Offset and Size Control
Besides synchronizing all SDRAM access activities, the
frame store controller also coordinates several offset and size
functions. These values are programmed into internal regis-
ters that control the setup of the Frame Store Controller.
Input horizontal offset, IHO is a ten bit value that sets the
horizontal displacement of the captured active video relative
to the horizontal sync as show in Figure 12.
Input vertical offset, IVO is a ten bit value that sets the verti-
cal displacement of the captured active video relative to the
vertical sync as show in Figure 12.
Figure 12. Input Offset and Size Definitions
Input horizontal active width, IHAW is the 10-bit terminal
count of the number of horizontal pixels to be inserted into
frame store memory. (see Figure 12)
Input lines sampled, ILS is the 10-bit terminal count of the
number of lines to be inserted into frame store memory fol-
lowing vertical scaling. (see Figure 12)
Output Offset and Size Control
Synchronization and timing of outgoing video pixel data is
predetermined by the selection of the video format. How-
ever, the location of the active video area must be selected by
programming the offset registers. Leading edges of outgoing
horizontal and vertical sync define the dimensions of the out-
going frame as shown in Figure 13. Offsets OVO and OHO
define the position of the active video area within the outgo-
ing frame.
Output horizontal offset, IHO is the 8-bit terminal count of
the horizontal displacement of the outgoing active video in
pixels relative to the leading edge of horizontal sync. (see
Figure 13)
Output vertical offset, IVO is the 8-bit terminal count of the
vertical displacement of the outgoing active video in pixels
relative to the beginning of vertical sync equalization pulses.
(see Figure 13)
Figure 13. Output Horizontal and Vertical
Offset Definitions
Incoming Hsync
IHO
IVO
ILS
IHAW
O
2366-12
Selected Active
Video Area
Incoming Active Video Area
Output Hsync
OHO
OVO
O
2366-13
Output Active
Video Area
Output Video Frame Area
Figure 11. Timing Parameter Definition, SDRAM Interface
2366-11
t
FDSU
t
FDHO
t
FCO
t
FAO
t
FDO
FSCK-OUT
CS
RAS
CAS
WE
DQM
A[11:0]
D[15:0]
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