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參數(shù)資料
| 型號： | TMC2376 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PC-to-TV Video Standards Converter(PC到TV視頻標準變換器) |
| 中文描述： | PC到電視視頻標準轉(zhuǎn)換器（電腦到電視視頻標準變換器） |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 233K |
| 代理商： | TMC2376 |
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TMC2376
PRODUCT SPECIFICATION
18
P
Black
100% Color Bars
75% Color Bars
Vertical Comb
(one green line per 11 pixels)
Horizontal Comb
(one green line per 11 pixels)
Red Gradient
(256 Steps)
Green Gradient
(256 Steps)
Blue Gradient
(256 Steps)
Grey Gradient
(256 Steps)
2366-05
Blue
Red
Magenta
Green
Cyan
Yellow
White
0
63
64
127
128
191
192
255
256
319
320
383
384
447
448
511
internally from the HS input. A digital output, CLAMP
which is HIGH when the clamp is active, may be used to
drive clamp circuits preceding external A/D converters when
the R
7-0
G
7-0
B
7-0
inputs are used.
Analog-to-Digital Converters
Setting the XA/D_SEL\ pin = H, selects the internal A/D
converters with inputs RGB while the R
7-0
G
7-0
B
7-0
digital
inputs become active outputs with undefined states. Bottom
reference voltage of the A/D converters is ground. Top refer-
ence voltage, VT is a high impedance input that is applied
via voltage followers to the reference ladder network of each
A/D converter. VT must be de-coupled with a 0.1
μ
F capaci-
tor to ground.
A stable voltage source greater than the input peak amplitude
must be connected to V
T
. Nominal level of V
T
is 0.75 volts,
slightly above the nominal to allow a margin between incom-
ing video levels and the conversion range. V
T
can be derived
from the internal reference voltage, V
REF
by splitting the
resistor connected to
RREF
as described in the Application
Notes section.
To avoid aliasing effects, incoming RGB video signals
should be filtered by a low pass filter prior to the AC cou-
pling capacitor. Filter cutout frequency should be set at half
the highest expected sampling rate of the A/D converter
clock, ADCK. A simple two element RC filter is adequate.
Phase of ADCK is set by the Command Register FAZE bit.
By flipping the phase of the sampling clock by 180
°
, the
sampling points can be positioned closer to the center of
incoming pixels. Figure 2 shows optimum sampling of VGA
pixels on the rising edge of the ADCLK signal, when syn-
chronous sampling is chosen.
Figure 2. FAZE Sets ADCK Sampling
Edge on Incoming Pixels
A/D converter power can be disconnected by setting the
Command Register ADCOFF bit.
24-bit Digital RGB Port
Extra pins are included on the TMC2376KB package to
incorporate a 24-bit TTL compatible RGB input port. Either
analog or digital inputs can be selected by the level on the
XA/DSEL\ pin. With the 24-bit RGB port enabled, incoming
pixels may be derived directly from an external digital RGB
source or from external analog RGB via triple 8-bit A/D con-
verters
Internal Bit Pattern Generator
BiPGen is the internal Bit Pattern Generator which outputs a
test pattern consisting of:
1.
Color Bars
2.
Gradient
3.
Impulses
BiPGen is initialized at power up and can be selected by set-
ting the BIPGEN bit in the Control Register, The pattern is
set as shown in Figure 3.
2366-04
ADCLK
VGAPIX
Figure 3. BiPGen Chart
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