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參數(shù)資料
| 型號： | TMC2376 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | PC-to-TV Video Standards Converter(PC到TV視頻標(biāo)準(zhǔn)變換器) |
| 中文描述： | PC到電視視頻標(biāo)準(zhǔn)轉(zhuǎn)換器（電腦到電視視頻標(biāo)準(zhǔn)變換器） |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 233K |
| 代理商： | TMC2376 |
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TMC2376
PRODUCT SPECIFICATION
12
P
Input Horizontal Samples Low (8)
7
IHS7
Input Horizontal Samples High (9)
7
0
Range:
{Min ADCK PLL Frequency * Input Horizontal Count (0xA,0xB) *(NTSC 4f
SC
Period - ( PAL_NTSC ( 0x10,0x11:Bit 1) *
(NTSC 4f
SC
Period - PAL 4f
SC
Period))):[{Max ADCK PLL Frequency * Input Horizontal Count (0xA,0xB) * (NTSC 4f
SC
Period -
(PAL_NTSC (0x10,0x11:Bit 1) * (NTSC 4f
SC
Period - PAL 4f
SC
Period))):[1022]}]}.
Note:
1. ADCK PLL frequency = 4f
SC
* IHS / IHC. Accounting for the maximum and minimum PLL VCO frequencies establishes the
limits on the range of IHS. In the range equation, the PAL_NTSC bit controls addition of the difference between NTSC and
PAL 4f
SC
clock periods.
Input Horizontal Count Low (A)
7
IHC7
Input Horizontal Count High (B)
7
0
Range:
{0:[511]}.
6
5
4
3
2
1
0
IHS6
IHS5
IHS4
IHS3
IHS2
IHS1
IHS0
6
0
5
0
4
0
3
0
2
0
1
0
IHS9
IHS8
Reg
9, 8
Bit#
1-0, 7-0
Name
IHS9-0
Description
Input horizontal line samples bits [9:0].
Terminal count
of the number of clocks per horizontal line between
incoming horizontal sync pulses. Internal ADCK phase-
locked loop is programmed with this value.
6
5
4
3
2
1
0
IHC6
IHC5
IHC4
IHC3
IHC2
IHC1
IHC0
6
0
5
0
4
0
3
0
2
0
1
0
0
IHC8
Reg
B, A
Bit#
0, 7-0
Bit Name
IHC8-0
Description
Input horizontal count bits [8:0] (read only).
Number of
4f
SC
clock pulses per horizontal line. 4f
SC
is the selected
4X subcarrier clock (17.734 MHz for PAL or 14.318 MHz
for NTSC). IHC can be read to determine the incoming
horizontal line frequency for auto selection of the incoming
video format.
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