
TMC2376
PRODUCT SPECIFICATION
3
P
Architectural Overview
Overall design structure is outlined in this section. Details
of how to use and setup the TMC2376 are included in the
Functional Description section.
RGB video inputs are asynchronously converted to either
NTSC/PAL, YUV or RGB video formats. Architecturally,
the TMC2376 is divided into five major sections:
Video Capture Engine
Clock Processor
Frame Store Controller
Video Encoder Engine
Serial Bus Interface
Besides power and a few external passive components, the
TMC2376 requires only a single 16M external SDRAM and
external clocks to implement a high quality video standards
converter.
Analog RGB inputs with separate horizontal and composite
sync signals are accepted. Analog video must be AC coupled
to allow clamping during the horizontal sync period. Digital
inputs must be 24-bit RGB clocked by external clock,
ADXCK.
A wide range of resolution formats can be accepted, includ-
ing VESA and industry standards such as 640x480, 800x600
and 1024x768. Incoming RGB signals are converted to
either the NTSC or PAL TV Standards. Output video format
can be selected to be either composite, Y/C, RGB or YUV.
Incoming frame rate can range from 56 to 95 Hz. The Video
Capture engine runs asynchronously relative to the Video
Encoder Engine. An external frame store memory separates
the two engines with write and read access controlled by the
TMC2376.
Transformation operations include overscan, underscan, pan
and zoom. Scaling operations are separated by the frame
store with vertical down-sampling incorporated into the Cap-
ture Engine and horizontal up-sampling incorporated into the
Encoder Engine.
Video Capture Engine
AC coupled RGB video inputs are clamped to ground. Triple
8-bit A/D converters digitize the analog RGB inputs at rates
of up to 50 Ms/s. Internal A/D sample clock, ADCK is
derived from a phase locked loop referenced to the leading
edge of horizontal sync. Either positive or negative sync
polarity is accepted.
The selected input (A/D converter outputs or TMC2376
digital RGB) is transcoded by the color matrix into the 16-bit
YCBCR422 format. Next, the Vertical Scaler reduces the
number of incoming video lines by the selected scaling
factor. Finally, the 3-line Flicker Filter averages lines to
eliminate flicker between horizontal lines or along
horizontal boundaries.
Frame Store Memory Controller
Inserted between the capture and the encoder engines, the
frame store has two functions: one is to act as a reservoir of
pixels to match the incoming frame rate the outgoing field
rate; the other is to support vertical scaling by allowing lines
to be written into the frame store intermittently, but read out
at a constant rate.
Frame store clock, FS_CK is derived from the CKNTSC
clock by a second phase locked loop that is referenced to the
4 fsc subcarrier clock.
Video Encoder Engine
Pixels are retrieved from the external frame store memory
asynchronously relative to the incoming frames. Outgoing
video timing is set to the selected TV standard, either NTSC
or PAL.
Incoming data sampling is normally set to fill complete lines
in the Frame Store Memory. Horizontal scaling is applied to
pixels exiting the Frame Store. Pixels may be routed through
either a digital video encoder or an YCBCR-to-RGB trans-
formation matrix. Either output is connected to a triple 9-bit
D/A converter to generate the video output which can be in
either CVBS, Y/C, RGB or YUV format.
Encoder Engine timing is derived from one of two 4x sub-
carrier sources: 14.31818 MHz CKNTSC for NTSC;
17.734475 MHz CKPAL for PAL.
Serial Control Port
TMC2376 setup is programmed by fourteen 10-bit registers
that are accessible via the I
2
C compatible serial port. Status
and Revision ID can also be read from the registers.