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參數(shù)資料
| 型號： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 9/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
17 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
A hum remover is implemented in the SOG. It removes completely the hum perturbation
on the rst or second edge of the horizontal sync pulse for digital video input like VESA,
and on the second edge only for analog video input signal like TV or HDTV.
The maximum hum perturbation is 250 mV (p-p) at 60 Hz to have a correct SOG
functionality.
[1]
Denitions:
Tvideo — Total time in 2 frames when video signal is strictly superior to black level.
Tline — Total time of 2 frames.
Tsync — Total time in 2 frames when the video signal is strictly inferior to black level.
8.6 Programmable coast
When the values of PRECOAST[2:0] = 0 and POSTCOAST[4:0] = 0, the coast pulse
equals the Vsync input.
When an interlaced signal is used, the regenerated coast pulse width may vary from one
frame to another of one Hsync pulse. In that case, the programmed value of
PRECOAST[2:0] needs to be increased by one compared to the expected minimum
number of Hsync coast pulses before the vertical sync signal.
8.7 Data enable
This signal qualies the active data period on the horizontal line. Pin DEO = HIGH during
the active display time and LOW during the blank time. The start of this signal can be
adjusted with bits HSYNCL[9:0] and HBACKL[9:0]. The length of this signal can be
adjusted with bits HDISPL[11:0].
8.8 Sync separator
The sync separator is compatible with TV, HDTV and VESA standards.
If the green video signal has composite sync on it (sync-on-green), the SOG function
allows to separate the Chsync and the active video part. The Chsync signal coming from
this SOG function is accessible through pin CSYNCO.
It is possible to extract the Hsync and the Vsync signals by using the sync separator from
this (C)Hsync signal coming from SOG or coming from the (C)Hsync input.
This function is able to get rid of the additional synchronization pulses in vertical blanking
like equalization or serration pulses.
Table 5.
Charge pump current programming[1]
BITS SOGI[1:0]
Maximum value
Standard
Tvideo / Tline
Tsync / Tline
00
83.5 %
14.8 %
TV standards and non-VESA
standards
01
86.0 %
12.6 %
all TV, HDTV and VESA standards
10
90.5 %
8.6 %
HDTV standards or non-VESA
standards
11
test mode
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相關代理商/技術參數(shù) |
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| TDA8755 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| TDA8757 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
| TDA8757HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
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