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參數(shù)資料
| 型號： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 27/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
33 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.15 Inverter register
4
CLPSEL1
can be used to select the clamp signal; see bit CLPSEL2
0 = PLL reference signal
1 = clamp input
3
CLPH
inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST (Table 46)
0 = clamp inhibited during Vsynco
1 = clamp active during Vsynco
2
CLPENL
denes if clamp input works on edge or on level
0 = on edge; for all frequencies (must be preferably chosen)
1 = on level; only for frequencies below 45 MHz to have proper clamp function
1
ICLP
dedicated for test mode; should be forced to logic 0
0
CLPT
denes if the test mode of the clamp is active
0 = not active
1 = active
Table 48.
CLAMP - clamp register (address 15h) bit description …continued
Bit
Symbol
Description
Table 49.
INVERTER - inverter register (address 16h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
COS
CLPS
CKREFOINV
DEOINVRGB
HSOINVRGB
VSOINVRGB
FIELDOINV
Reset
X0
0
Access
WWW
W
Table 50.
INVERTER - inverter register (address 16h) bit description
Bit
Symbol
Description
7
-
not used
6
COS
enables the COAST input signal to be inverted
0 = non-inverted
1 = inverted
5
CLPS
enables the CLAMP input signal to be inverted
0 = non-inverted
1 = inverted
4
CKREFOINV
enables the output CKREFO to be inverted
0 = non-inverted
1 = inverted
3
DEOINVRGB
enables the output DEO to be inverted
0 = non-inverted
1 = inverted
2
HSOINVRGB
enables the output HSYNCO to be inverted
0 = non-inverted
1 = inverted
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