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| 型號(hào)： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 26/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
32 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.13 Vertical sync selection register
9.14 Clamp register
Table 45.
VSYNCSEL - vertical sync selection register (address 14h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
TSTCOAST
COE
VSS
COSSEL2
COSSEL1
Reset
X
0
0000
Access
WWW
W
WWWW
Table 46.
VSYNCSEL - vertical sync selection register (address 14h) bit description
Bit
Symbol
Description
7 to 5
-
not used
4
TSTCOAST
switches a multiplexer to select the output signal on pin VSYNCO
0 = output of the separator function
1 = output of the coast function
3
COE
enables coast mode
0 = coast mode
1 = no coast mode
2
VSS
enables VSYNC input signal to be inverted
0 = non-inverted
1 = inverted
1
COSSEL2
selects signal for coast PLL mode
0 = signal selected with bit COSSEL1
1 = pin coast
0
COSSEL1
can be used for the coast PLL mode; see bit COSSEL2
0 = VSYNC input
1 = VSYNC from the sync separator
Table 47.
CLAMP - clamp register (address 15h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
HSOSEL
CLPSEL2
CLPSEL1
CLPH
CLPENL
ICLP
CLPT
Reset
X
0100000
Access
WWWWWWWW
Table 48.
CLAMP - clamp register (address 15h) bit description
Bit
Symbol
Description
7
-
not used
6
HSOSEL
denes the signal on the output HSYNCO; see Section 8.3
0 = Hsync from the Hcounter
1 = Ckref is reference of the PLL
5
CLPSEL2
can be used to select the clamp signal
0 = Hsync signal generated by the pixel counter
1 = signal selected with bit CLPSEL1
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