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| 型號(hào)： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 20/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
27 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.6 Sync-on-green register
9.7 PLL control register
Table 26.
SOG - sync-on-green register (address 09h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DO
UP
FTRILEVEL
STRILEVEL
CKREFS
SOGSEL
SOGI1
SOGI0
Reset
0
0000
0
1
Access
W
WWWW
W
Table 27.
SOG - sync-on-green register (address 09h) bit description
Bit
Symbol
Description
7
DO
test bit for forcing charge pump current down
0 = reset value
1 = forcing down
6
UP
test bit for forcing charge pump current up
0 = reset value
1 = forcing up
5
FTRILEVEL
denes the 3-level function mode
0 = automatic 3-level
1 = level selection with bit STRILEVEL
4
STRILEVEL
forces the state of 3-level function
0 = not 3-level mode
1 = 3-level mode
3
CKREFS
enables the PLL Ckref signal to be selected
0 = same as input
1 = input inverted
2
SOGSEL
enables the reference PLL between HSYNC input and SOG input to be selected
0 = HSYNC input
1 = SOG input
1 to 0
SOGI[1:0]
denes the SOG charge pump current; values are given in % of sync pulse/line length
00 = 14.8 % maximum (TV standards) and non-VESA standards
01 = 12.6 % maximum (all standards)
10 = 8.6 % maximum (HDTV standards) and non-VESA standards
11 = 0 test mode
Table 28.
PLLCTRL- PLL control register (address 0Ah) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
IP1
IP0
Z2
Z1
Z0
DR2
DR1
DR0
Reset
01011100
Access
WWWWWWWW
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