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參數(shù)資料
| 型號： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
29 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.9 PLL divider registers
Table 32.
Phase registers bits
PA4
PA3
PA2
PA1
PA0
Phase shift (deg)
000000
0
1
11.25
::::::
1
0
337.50
1
348.75
Table 33.
VCO gain control
VCO2
VCO1
VCO0
VCO gain
(MHz/V)
Pixel clock frequency
(MHz)
0
13
12to22
0
1
30
22to45
0
1
0
60
45to62
0
1
60
62to85
1
0
105
85 to 120
1
0
1
105
120 to 176
1
0
135
176 to 270
1
no oscillation
-
Table 34.
DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CKEXT
SCHCKREFO
EPSI1
EPSI0
DI11
DI10
DI9
DI8
Reset
0
000110
Access
W
WWWWWW
Table 35.
DIVMSB - PLL divider ratio (MSB) register (address 0Ch) bit description
Bit
Symbol
Description
7
CKEXT
external clock selection
0 = internal PLL
1 = external clock
6
SCH
CKREFO
shift of pixel counter reference (Ckref) with one clock pixel period
0 = not active
1 = active
5 to 4
EPSI[1:0]
enables the resynchronization edge of CKREFO to be selected; they are test bits
00 = reset value for proper operation
3 to 0
DI[11:8]
PLL divider ratio; these are the 4 MSBs of the 12-bit value; see Table 38
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