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參數(shù)資料
| 型號(hào)： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 6/57頁 |
| 文件大小： | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
14 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
8.1.1.2
Power-down mode
In Power-down mode the status of the blocks is as follows:
All digital inputs and outputs are in high-impedance state
All blocks are inactive (I2C-bus, activity detection, ADCs, etc.)
Analog output is left uncontrolled
I2C-bus is left in high-impedance state.
8.2 Analog video input
The RGB/YUV video inputs are externally AC coupled and are internally DC polarized.
The synchronization signals are also used by the device as input for the internal PLL and
the automatic clamp.
8.2.1 Analog multiplexers
The TDA8754 has two analog inputs (RGB input 1 and RGB input 2) selectable via the
I2C-bus.
The sync management can be achieved in several ways:
Choice between two analog inputs HSYNC and two analog inputs VSYNC
Choice between two analog inputs CHSYNC
Choice between two analog inputs SOG.
8.2.2 Activity detection
When a signal is connected or disconnected on pins HSYNC1(2), CHSYNC1(2),
VSYNC1(2) and SOG1(2), then bit HPDO is set to logic 1 and pin HPDO is set to HIGH to
advise the user of a change. Bit HPDO is set to logic 0 and pin HPDO is set to LOW when
register ACTIVITY2 has been read.
When the synchronization pulse on pin SOG is 3-level, the system will automatically be
able to detect that a 3-level sync is present and will force bit 3LEVEL to logic 1. It is
possible to disable this function with bit FTRILEVEL.
When an interlaced signal is detected, bit ACFIELD is set to logic 1. When the signal
detected is progressive, this bit is set to logic 0. Any change in this bit results into setting
bit HPDO = 1 and pin HPDO = HIGH.
A eld detection unit is available on pin FIELDO which output is given by the sync
separator. The eld identity is given by pin FIELDO. This pin gives the eld of interlaced
signal input.
An automatic polarity detection is also available on pins HSYNC1(2), VSYNC1(2) and
CHSYNC1(2). The output on pin HPDO is not affected by the change of polarity of these
inputs.
8.2.3 ADC
The three ADCs are designed to convert R, G and B (or Y, U and V) signals at a
maximum frequency of 270 Msample/s. The ADC input range is 1 V (p-p) full-scale and
the pipeline delay is 2 ADC clock cycles from the input sampling to the data output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TDA8754HL/14/C1 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| TDA8754EL/11/C1 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| TDA8754EL/27/C1 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
| TDA8754HL/11/C1 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| TDA8754EL/25 | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBGA208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA8755 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755T | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
| TDA8755TD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TV/Video Signal Processor |
| TDA8757 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
| TDA8757HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Triple 8-bit ADC 170 Msps |
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