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| 型號： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數(shù)： | 31/57頁 |
| 文件大小： | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
37 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.20 Internal oscillator register
9.21 Power management register
1
OUTOSCILL
enables pin CKDATA to be switched with a multiplexer to have signal Ckdata or the internal
oscillator on the output
0 = Ckdata
1 = for test
0
CKOENRGB
enables the output CKDATA to be set to high-impedance
0 = active signal
1 = high-impedance
Table 58.
CLKOUTPUT - clock output register (address 1Ah) bit description …continued
Bit
Symbol
Description
Table 59.
INTOSC - internal oscillator register (address 1Bh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
------
SWITCHOSC
INTOSCOFF
Reset
XXXXXX
0
Access
WWWWWW
W
Table 60.
INTOSC - internal oscillator register (address 1Bh) bit description
Bit
Symbol
Description
7 to 2
-
not used
1
SWITCHOSC
enables a multiplexer to be switched; signal insertion on the input of the separator and
coast block, between the internal oscillator and pin CKEXT
0 = normal case; if this bit is switched from logic 1 to logic 0, then an internal reset of the
coast, activity detection and sync separator is done
1 = test mode
0
INTOSCOFF
disables the internal oscillator for the separator function, the coast gate and activity
detection
0 = active; if this bit is switched from logic 1 to logic 0, then an internal reset of the coast,
activity detection and sync separator is done
1 = disabled
Table 61.
PWRMGT - power management register (address 1Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
----
SHCKDMX
SHCKADC
STBY
DVIRGB
Reset
XXXX
0000
Access
WWWWWWWW
Table 62.
PWRMGT - power management register (address 1Eh) bit description
Bit
Symbol
Description
7 to 4
-
not used
3
SHCKDMX
test bits; should be set to logic 0 for proper operation
2
SHCKADC
test bits; should be set to logic 1 for better performances
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