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參數資料
| 型號： | TDA8754HL/27/C1 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, SOT486-1, LQFP-144 |
| 文件頁數： | 30/57頁 |
| 文件大?。?/td> | 259K |
| 代理商： | TDA8754HL/27/C1 |
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TDA8754_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 3 May 2007
36 of 57
NXP Semiconductors
TDA8754
Triple 8-bit video ADC up to 270 Msample/s
9.19 Clock output register
5
DEOENRGB
enables the output DEO to be set to high-impedance
0 = active signal
1 = high-impedance
4
HSOENRGB
enables the output HSYNCO to be set to high-impedance
0 = active signal
1 = high-impedance
3
HPDOEN
enables the output HPDO to be set to high-impedance
0 = active signal
1 = high-impedance
2
VSOENRGB
enables the output VSYNCO to be set to high-impedance
0 = active signal
1 = high-impedance
1
CLPOEN
enables the output CLPO to be set to high-impedance
0 = active signal
1 = high-impedance
0
FIELDOEN
enables the output FIELDO to be set to high-impedance
0 = active signal
1 = high-impedance
Table 56.
OUTPUTEN2 - output enable 2 register (address 19h) bit description …continued
Bit
Symbol
Description
Table 57.
CLKOUTPUT - clock output register (address 1Ah) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
CKSELRGB
DLYCLKRGB
CKDATINV
OUTOSCILL
CKOENRGB
Reset
XXX
0
1
Access
EW
W
Table 58.
CLKOUTPUT - clock output register (address 1Ah) bit description
Bit
Symbol
Description
7 to 5
-
not used
4
CKSELRGB
enables the selection of the signal on the pin CKDATA
0 = clock of output buffers; signal Ckdata
1 = pixel clock of the converter; signal Ckadco
3
DLYCLKRGB
enables a delay of 2 ns to be added to the clock Ckdata
0 = no delay
1 = 2 ns delay
2
CKDATINV
enables the polarity of the output CKDATA to be inverted
0 = non-inverted
1 = inverted
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相關代理商/技術參數 |
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| TDA8755 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:YUV 8-bit video low-power analog-to-digital interface |
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