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參數(shù)資料
| 型號： | TCM4400EGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 8/64頁 |
| 文件大小： | 888K |
| 代理商： | TCM4400EGGM |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
voltage references
REFERENCE
MIN
TYP
MAX
UNIT
VGAP
Voltage on band gap (used for all other references)
1.16
1.22
1.28
Vdc
K
μ
F
ms
Band gap output resistance
200
Band gap external decoupling capacitance
0.1
Band gap start time ( bit CHGUP=0 )
100
Band gap start time ( bit CHGUP=1)
2.5
ms
VREF
Voltage reference of GMSK internal ADC and DAC : VVREF
Voltage reference output resistance
1.66
1.75
1.84
Vdc
K
μ
F
ms
200
Voltage reference external decoupling capacitance
0.1
Voltage reference start time ( bit CHGUP=0 )
300
Voltage reference start time ( bit CHGUP=1)
10
ms
VMID
Common-mode reference for baseband uplink: VVMID
(Bit SELVMID=0)
Common-mode reference for baseband uplink:
VVMID (Bit SELVMID=1)
Load resistance on Vmid output
–10%
Vdd/2
10%
Vdc
1.25
1.35
1.45
Vdc
K
Vdc
10
MICBIAS
Microphone-driving voltage (Bit MICBIAS=0)
1.80
2.00
2.20
Microphone-driving voltage(Bit MICBIAS=1)
2.25
2.5
2.75
Vdc
μ
A
μ
A
Vdc
μ
F
K
Microphone-bias current drive capability (Bit MICBIAS= 1)
450
500
Microphone-bias current drive capability (Bit MICBIAS=0 )
350
400
ADCMID
DC bias reference of the auxiliary ADCs
–10%
Vdd/2
10%
ADCMID external decoupling capacitance
0.1
IBIAS
Bias current adjust external resistance
100
master clock input (MCLK)
PARAMETER
MIN
NOM
MAX
UNIT
Master clock signal frequency
13
MHz
Master clock duty cycle (Sinewave)
40%
60%
Maximum peak-to-peak amplitude
1.3
Vpp
Minimum peak-to-peak amplitude
0.5
Vpp
Common-mode input voltage
VSS +0.5
4.1
VDD –0.5
6.5
Vdc
Input resistance at 13MHz (MCLK to ground)
5
K
pf
Input capacitance at 13 MHz (MCLK to ground)
12.5
15
18
baseband uplink path
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I and Q D/A converters resolution
8
bit
Dynamic range on each output
Differential output dynamic range with OUTLEV bit = 0
Differential output dynamic range with OUTLEV bit = 1
Centered on VVMID
BULQP-BULQN or BULIP-BULIN
VVREF
2 x VVREF
8/15 x VVREF
Vpp
Vpp
BULQP-BULQN or BULIP-BULIN
Vpp
k
pF
Output load resistance, differential
10
Output load capacitance, differential
50
Output common-mode voltage
Programmable by bit SELVMID
VVMID
Hi-Z
V
I & Q output state in power down
Initial value after reset and at beginning of each burst are BULIP–BULIN=VREF and BULQP–BULQN=0 corresponding to a phase angle of 0
°
.
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