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參數(shù)資料
| 型號： | TCM4400EGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大小： | 888K |
| 代理商： | TCM4400EGGM |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
RF power control (continued)
When APCMODE is one (see Figure 13) the APC output is given by formula
APCout = ( Shape value * Level value ) + Offset
BULON
BENA
APC OUT
Level 1
Level 255
Level 0
Offset = 120 mV
Figure 13. APC Output When APCMODE = 1
Power down is controlled with two bits. The first bit (APCW of AUXCTL2 register) determines whether the APC
can be powered down by activating external GSM transmit window activation (BULON): The second bit (APCPD
of AUXCTL2 register) controls the activation of APC function. See the topic, power-down functional description
for more details about power-down control. The auxiliary analog functions of the GSM baseband A/D and D/A
conversions are independently powered from the AV
DD5
terminal.
monitoring
The monitoring section includes a 10-bit A/D converter and one result register that allows monitoring of five
external analog values such as the temperature and the battery voltage. The selection of the input and reading
of the control registers is done using the serial interfaces.
The selection of the input channel is done with the bits ADCCH0 – ADCCH2 of the AUXCTL1 register; the data
is read from the AUXADC register. Power down is controlled with two bits. The first bit (ADCPN of AUXCTL1
register) determines whether the A/D converter can be powered down from the external PWRDN terminal. The
second bit (ADCPD of AUXCTL1 register) controls the activation of the A/D conversion function. See the topic,
power-down functional description for more details about power-down control.
Conversion is started with a write access to the AUXCTL1 register. During the conversion, the ADCEOC bit of
BSTATUS register stays at 1 and resets to 0 when the converted data is loaded into the AUXADC register. This
way the power consumption of the main parts of the converter is limited to the useful part of the conversion time.
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