參數(shù)資料
型號： TCM4400EGGM
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路
文件頁數(shù)： 34/64頁
文件大?。?/td> 888K
代理商： TCM4400EGGM
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
voice downlink path
The voice downlink path receives speech samples at an 8-kHz rate from the voice serial interface and converts
them to analog signals to drive the external speech transducer.
The digital speech coming from the voice serial interface is first fed to a speech-digital infinite-duration impulse
response (IIR) filter, which has two functions (see Figure 15). The first function is to interpolate the input signal
and increase the sampling rate form 8 kHz up to 1 MHz to permit D/A conversion by an oversampling digital
modulator. The second function is to band limit the speech signal, using both low-pass and high-pass transfer
functions.
The interpolated and band-limited signal is fed to a second-order sigma-delta modulator and sampled at 1 MHz
to generate a 1-bit oversampled signal that drives a 1-bit D/A converter.
Due to the oversampling conversion, the analog signal obtained at the output of the one-bit D/A converter is
mixed with high frequency noise. This noise is filtered by a switched-capacitor third-order low-pass filter and
the remaining signal is fed to a programmable gain amplifier (PGA) to adjust the volume control. Volume control
is done in 6-dB steps from 0 dB through –24 dB; in the mute state, attenuation is higher than 40 dB. A fine
adjustment of gain is possible from –6 to +6 dB in 1-dB steps to calibrate the system, depending on the earphone
characteristics. This configuration is programmed using the VBCTL2 register.
The PGA output is fed to two output stages: the earphone amplifier that provides a full differential signal on the
terminals EARP/EARN and an auxiliary output amplifier that provides a single-ended signal on terminal AUXO.
Both earphone and auxiliary output amplifiers can be active at the same time. The downlink voice path can be
powered down with bit VDLON of the VBCTL2 internal register.
A side-tone path is connected between the output of the voice uplink PGA and the input of the voice downlink
PGA. This path provides seven programmable gains (+1 dB, –2dB, –5 dB, –8 dB, –11 dB, –14 dB, –17 dB,
–20 dB, –23 dB) and one mute position. Side-tone path gain can be selected by a programming bit at register
address 23.
Smoothing
Filter
Volume Count
and PGA
Earphone
Amplifier
0 dB
Auxiliary
Amplifier
–6 dB
One-Bit DAC
Low-Pass Filter
+3 dB
fs1 = 1 MHz
Sigma_Delta
Modulator
–3 dB
fs2 = 40 KHz
SINC
Interpolation
Filter
fs3 = 8 KHz
From Voice
Serial Interface
EARP
EARN
AUXO
IIR
Bandpass
Filter
0 +24 dB and
–6 +6 dB
Side-Tone
–23 to+1dB
From Voice Uplink PGA
Figure 15. Downlink Path Block Diagram
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