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參數(shù)資料
| 型號： | TCM4400EGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 28/64頁 |
| 文件大?。?/td> | 888K |
| 代理商： | TCM4400EGGM |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
baseband downlink path (continued)
The antialiasing filter is followed by a third-order sigma-delta modulator that performs A/D conversion at a
sampling rate of 6.5 MHz. The A/D converter provides 3-bit words that are fed to a digital filter (see Figure 9)
that performs the decimation by a ratio of 24 to lower the sampling rate down to 270.8 KHz and the channel
separation by rejecting enough of the adjacent channels to allow the demodulation performances required by
the GSM specification. Figure 10 shows the frequency response curve for the downlink digital filter and Figure
11 shows the in-band response curve for the same digital filter.
The baseband downlink path includes an offset register in which the value representing the channel dc offset
is stored; this value is subtracted from the output of the digital filter before transmitting the digital samples to
the DSP using the serial interface. Upon reset, the offset register is loaded with 0 and updated with the BCAL
calibrating signal (see Figure 2).
The content of the offset register results from a calibration sequence. The input BDLIP is shorted with the input
BDLIN, and the input BDLQP is shorted with the input BDLQN. The digital outputs are evaluated and the values
are stored in the corresponding offset registers in accordance with the dc offset of the GSM baseband and voice
A/D and D/A downlink path. When the external autocalibration sequence is selected, the inputs BDLIP and
BDLIN and the inputs BDLQP and BDLQN remain connected to the external circuitry. The digital outputs are
evaluated, and the values stored in the corresponding offset registers take into account the dc offset of the
external circuitry.
Timing control of the baseband downlink path is controlled by bits BDLON (downlink on), BCAL (calibration),
and BENA (enable) when BDLON is active (please see timing interface section
)
. BDLON controls the power
up of the baseband downlink path; BCAL controls the start and duration of the autocalibration sequence (which
can be internal or external depending on bit EXTCAL of PWDNRG1 register); and BENA controls the beginning
and the duration of data transmission to the DSP by using the DSP serial interface. To avoid transmission of
irrelevant data corresponding to the settling time of the digital filter, the eight first I&Q computed samples are
not sent to the DSP; first data are transmitted though the DSP interface about 30
μ
s after the BENA rising edge.
The power-down sequence is controlled with two bits. The first bit (BBDLW of PWDNRG1 register) determines
whether the baseband downlink path can be powered down with external GSM receive window activation
(BDLON): The second bit, BBDLPD of register PWDNRG1, controls the activation of the baseband downlink
path. Please see power-down functional descriptionsection for more details about power-down control.
Antialiasing
Filter
Sigma-Delta
Modulator
SINC
Filter
Sigma-Delta
Modulator
SINC
Filter
FIR
Filter
FIR
Filter
Offset
Calibration
Offset
Register
SUB
Offset
Calibration
Offset
Register
SUB
Antialiasing
Filter
fs3 = 270.8 kHz
fs2 = 1.08 MHz
fs1 = 6.5 MHz
BDLIP
BDLIN
BDLQP
BDLQN
To Baseband
Serial Interface
Figure 9. Functional Structure of the Baseband Downlink Path
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