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參數(shù)資料
| 型號： | TCM4400EGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 888K |
| 代理商： | TCM4400EGGM |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
44
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
BDLON
BCAL
BULON
BENA
DLON
DLCAL DLREC
ULON
ULCAL ULSEND
CKDL
CKUL
Figure 17. Timing Interface
DSP/MCU serial interface operation and format
The DSP/MCU serial interface configures the GSM baseband, the voice A/D and D/A converters (read and write
operation in internal registers), and transmits RF data to the DSP during the reception of a burst by the downlink
path of the GSM baseband and voice A/D and D/A circuitry.
During reception of a burst (bit DLR of the status register is 1) and DSP serial interface and associated internal
bus are dedicated to the transfer of RF data from the GSM baseband A/D and D/A converters to the DSP. During
this period only a write operation of internal registers can be done through the DSP serial interface. However,
all registers can be accessed by the serial MCU interface.
During transmission of a burst (bit ULX of the status register is 1) no read or write operation can be done in the
registers of the baseband uplink part of the GSM baseband, APC RAM, and APC shape register.
Writing or reading registers using the serial interface is done by transferring 16-bit words to the serial interface.
Each word is split into three fields as shown in Table 4.
Table 4. Read/Write Data Word
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áááááááááááááááááááááááááááááááá
DATA
ADDRESS
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1 / 0
When writing to internal registers observe the following convention:
Bit 0
: A 0 indicates a write operation.
Bits 1 to 5
: This field contains the address of the register to be accessed.
Bits 6 to 15
: This field contains the data to be written into the internal register.
When reading from internal registers observe the following convention:
Bit 0
: A 1 indicates a read operation.
Bits 1 to 5
: This field contains the address of the register to be accessed.
Bits 6 to 15
: This field is an irrelevant status in a read request operation.
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