參數(shù)資料
型號(hào)： TCM4400EGGM
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路
文件頁數(shù)： 59/64頁
文件大小： 888K
代理商： TCM4400EGGM
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
59
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
baseband status register
The baseband status register stores the baseband status as described in Table 35.
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DLR:
This bit is set to 1 during conversion of a burst in the downlink path.
BSTATUS: BASEBAND STATUS REGISTER
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ADDRESS: 22
R
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DLCAL:
This bit is set to 1 during offset calibration of the downlink path.
DLON:
When set to 1, it indicates that the downlink path is powered on.
ULX:
This bit is set to 1 during transmission of the burst in the uplink path.
ULCAL:
This bit is set to 1 during offset calibration of the uplink path.
ULON:
When set to 1, it indicates that the uplink path is powered on.
BUFPTR:
When set to 1, it indicates that the pointer of the burst buffer is at address zero.
RAMPTR:
When set to 1, it indicates that the pointer of the APC RAM is at address zero.
ADCEOC:
(ADC-end of conversion) when this bit is set to 1, an ADC conversion is in process.
Voiceband control register 4 (address 23)
Voiceband control register 4 (VBCTL4) is a read/write register (see Table 36) and contains the four programming
bits of VDLST as shown in Table 37.
Table 36. Voiceband Control Register 4
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R=0
R=0
R=0
R=0
R=0
R=0
R/W
R/W
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0
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VDLST3
0
VDLST2
VDLST1
1
VDLST0
–8 dB
SIDE TONE GAIN
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0
1
0
–17 dB
1
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0
0
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0
1
0
–5 dB (nominal)
1
0
0
–2 dB
0
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