參數(shù)資料
型號： TCM4400EGGM
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路
文件頁數(shù)： 42/64頁
文件大?。?/td> 888K
代理商： TCM4400EGGM
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
serial interface (continued)
Table 2. Microcontroller Clocking Schemes
UPOL
UPHA
MCU CLOCKING SCHEME
1
1
Falling edge without delay
1
0
Falling edge with delay
0
1
Rising edge without delay
0
0
Rising edge with delay
DSP/MCU serial interface
The DSP/MCU serial interface not only configures the GSM baseboard and voice A/D and D/A conversion but
also transmits data to the DSP during downlink burst reactions. The following paragraphs describe the operation
of the serial interface in more detail.
DSP serial digital interface
The DSP serial digital interface (Figure 16) is used to transfer the baseband transmit and receive data, and it
is also used to access all internal programming registers of the device (baseband codec, voice codec, and
auxiliary RF functions). The format for the serial interface is 16 bits.
The baseband serial digital interface is a bidirectional (transmit/receive) serial port. Both receive and transmit
operations are double buffered and permit a continuous communication stream (16-bit data packets). The serial
port is fully static and functions with any arbitrary, low-clocking frequency.
Six terminals are used for the serial port interface (see Figure 4 for timing diagram). BCLKR is an I/O port for
the serial clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and
the clock frequency is set to MCLK/3 (4.333 MHz with MCLK = 13 MHz); the clock signal is running permanently.
The port BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is
provided by the DSP. It can run in burst mode to reduce power consumption. The receive frame synchronization
(BFSR) is used to identify the beginning of a data packet transfer on port BDR.
The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used
to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice
A/D and D/A converters with a MCLK frequency. The clock signal BCLKX can run in burst mode or continuous
mode, depending on the BCLKMODE bit. The downlink data bus (BFSX, BCLKX, BDX) can be driven to VSS
or placed in a high-impedance state when no data is to be transferred to the DSP. The BCLKDIR bit of the
BCTLREG register controls the direction of the BCLKR clock.
As with the voice serial interface, on extra clock cycle must be generated because the last 16-bit word received
on the DSP serial interface is latched on the next two falling BCLKR edges following the LSB. As for the voice
serial interface, one extra clock period is generated on the BCLKX before the first synchronization BFSX of the
downlink data sequence.
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