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參數資料
| 型號： | TCM4400EGGM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT |
| 中文描述： | 的GSM / DCS的基帶和語音的A / D和D / A射頻接口電路 |
| 文件頁數： | 45/64頁 |
| 文件大小： | 888K |
| 代理商： | TCM4400EGGM |
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TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
45
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Read operation from the downlink baseband codec is done using the TX part of the DSP/MCU serial interface
in the following 16-bit word format given in Table 5.
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During reception of a burst, transfer of RF data from the downlink baseband codec is done using the transmit
part of the DSP serial interface in the following 16-bit word format: As the I and Q samples are coded with 16-bit
words, the data rate is 270833
×
16
×
2 which equals 8.66 Mbps. I & Q samples are differentiated by setting the
LSB to zero for I samples and to one for Q samples. Since the digital clock MCLK is 13 MHz, transfer is done
at 13 Mbps in burst mode. During burst reception the DSP serial interface is idled about 33% of the time.
DATA
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ADDRESS
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A4
A3
A2
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DSP/MCU serial interface registers
DATA
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I/Q
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15
14
13
12
11
10
9
8
7
6
5
D5
4
D4
3
D3
2
1
0
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The following internal register buffers are accessed using the DSP/MCU serial interface during manual
operation of the TCM4400E.
baseband uplink ramp delay register
Each bit position of the baseband uplink ramp-delay register is given in Table 7.
Table 7. Uplink Ramp-Delay Register
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DELU0 to DELU3
: Value of the delay of ramp-up start versus the rising edge of BENA
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DELD0 to DELD3
: Value of the delay of ramp-down start versus the falling edge of BENA
IBUFPTR
: Writing a 1 in this bit initializes the pointer of the burst buffer to the base address.
(This is not a toggle bit and has to be set back to 0 to allow writing into the burst
buffer).
RESERVD
: Reserved bits for testing purposes
R/W
: A 1 indicates a read operation; a 0 indicates a write operation.
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