參數(shù)資料
型號(hào)： TCM4400EGGM
廠商： Texas Instruments, Inc.
英文描述： GSM/DCS BASEBAND AND VOICE A/D AND D/A RF INTERFACE CIRCUIT
中文描述： 的GSM / DCS的基帶和語(yǔ)音的A / D和D / A射頻接口電路
文件頁(yè)數(shù)： 21/64頁(yè)
文件大?。?/td> 888K
代理商： TCM4400EGGM
TCM4400E
GSM/DCS BASEBAND AND VOICE A/D
AND D/A RF INTERFACE CIRCUIT
SLWS082A – JULY 1999 – REVISED MARCH 2000
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
downlink timing considerations
Figure 2 shows the timing diagram for downlink operation.
Timing control of the baseband downlink path is controlled by bits DLON (downlink on), BCAL (calibration) and
BENA (enable) when BDLON is active (see the topic, timing and interface
)
. BDLON controls the power up of
the baseband downlink path, BCAL controls the start and duration of the autocalibration sequence, and BENA
controls the beginning and the duration of data transmission to the DSP, using the DSP serial interface.
The power-down sequence is controlled with two bits, the first bit (BBDLW of PWDNRG1 register) determines
whether the baseband downlink path can be powered down with external GSM receive window activation
(BDLON); the second bit (BBDLPD of PWDNRG1 register) controls the activation of the baseband downlink
path. See the topic, power-down functional description for more details about power-down control.
tw3
tsu6
BDLON
BCAL
DATAOUT
tsu4
tsu5
th4
th5
BENA
tw4
Figure 2. Downlink Timing Sequence
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