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| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 89/248頁 |
| 文件大小： | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
79
Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used
to provide added protection against false frame alignment. The sources for the Si bits that are transmitted to the
line are the following:
1.
CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of
all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames.
2.
The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0)
1
.
This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where
frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state fol-
lowed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0
state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever
this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition
(indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment
state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the
transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the
transmit framer resumes normal operations.
3.
CEPT with CRC-4
2
: manual transmission of E bit = 0:
A. If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and
the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit).
B. If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is transmitted
in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmitted in frame
15.
4.
CEPT with CRC-4
2
, automatic transmission of E bit = 0:
A. Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section
2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28
bit 3 = 1.
B. Optionally, as described in ITU Rec. G.704 Section 2.3.3.4, both E bits are set to 0 while in a received loss
of CRC-4 multiframe alignment state
3
if FRM_PR28 bit 4 = 1.
C. Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU
Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multiframe
alignment state
3
if FRM_PR28 bit 5 = 1.
Otherwise, the E bits are transmitted to the line in the 1 state.
1.Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx
(binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
2.The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment.
3.Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is established, then and
only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of
LFA and LTS0MFA or in a state of LTS0MFA only, but cannot be in a state of LFA only.
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