參數(shù)資料
型號(hào)： T7633
廠商： Lineage Power
英文描述： Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器)
中文描述： 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器）
文件頁(yè)數(shù)： 24/248頁(yè)
文件大小： 1459K
代理商： T7633
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
14
Lucent Technologies Inc.
Feature Descriptions
(continued)
T1/E1 Framer Features
(continued)
I
Signaling:
— DS1: extended superframe 2-state, 4-state, and
16-state per-channel robbed bit.
— DS1: D4 superframe 2-state and 4-state per-
channel robbed bit.
— DS1: SLC-96 superframe 2-state, 4-state, 9-state,
and 16-state per-channel robbed bit.
— DS1: channel-24 message-oriented signaling.
— ITU CEPT: channel associated signaling (CAS)
and T7230A mode common channel signaling
(CCS).
— ITU CEPT: international remote switching module
(IRMS).
— Transparent (all data channels).
I
Alarm reporting, performance monitoring, and main-
tenance:
— ANSI T1.403-1995, AT&T TR 54016, and ITU
G.826 standard error checking.
— Error and status counters:
1. Bipolar violations.
2. Errored frame alignment signals.
3. Errored CRC checksum block.
4. CEPT: received E bit = 0.
5. Errored, severely errored, and unavailable
seconds.
— Selectable errored event monitoring for errored
and severely errored seconds processing with
programmable thresholds for errored and severely
errored second monitoring.
— CEPT: Selectable automatic transmission of E bit
to the line.
— CEPT: Sa6 coded remote end CRC-4 error E bit =
0 events.
— Programmable automatic and on-demand alarm
transmission:
1. Automatic transmission of remote frame alarm
to the line while in loss of frame alignment
state.
2. Automatic transmission of alarm indication
signal (AIS) to the system while in loss of
frame alignment state.
— Multiple loopback modes.
— Optional automatic line and payload loopback ac-
tivate and deactivate modes.
— CEPT nailed-up connect loopback and CEPT
nailed-up broadcast transmission TS-X in TS-0
transmit mode.
— Selectable test patterns for line transmission.
— Detection of framed and unframed pseudorandom
and quasi-random test patterns.
— Programmable squelch and idle codes.
I
System interface:
— Autonomous transmit and receive system interfac-
es.
— Independent transmit and receive frame synchro-
nization input signals.
— Independent transmit and receive system inter-
face clock.
— 2.048 Mbits/s, 2.048 MHz concentration highway
interface (CHI) default mode.
— Optional 4.096 Mbits/s and 8.192 Mbits/s data
rates.
— Optional 4.096 MHz, 8.192 MHz, and 16.384 MHz
frequency system clock.
— Programmable clock edge for latching frame syn-
chronization signals.
— Programmable clock edge for latching transmit
and receive data.
— Programmable bit and byte offset.
— Programmable CHI master mode for the genera-
tion of the transmit CHI FS from internal logic with
timing derived from the receive line clock signal.
I
Digital phase comparator for clock generation in the
receive and transmit paths.
Facility Data Link Features
I
HDLC or transparent mode.
I
Automatic transmission of the ESF performance
report messages (PRM).
I
Detection of the ESF PRM.
I
Detection of the ANSI ESF FDL bit-oriented codes.
I
64-byte FIFO in both transmit and receive directions.
I
Programmable FIFO full- and empty-level interrupt.
I
SLC-96: FDL transmit and receive register access of
D bits.
User-Programmable Microprocessor Inter-
face
I
33 MHz read and write access with no wait-states.
I
12-bit address, 8-bit data interface.
I
Programmable Intel or Motorola interface modes.
I
Demultiplexed or multiplexed address and data bus.
I
Directly addressable internal registers.
I
No clock required.
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