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| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 105/248頁(yè) |
| 文件大小： | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
May 1998
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
95
Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
Alarm Definition
(continued)
10.
Failed state
alarm or the
unavailable state alarm
, FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit 7.
This alarm is defined as the unavailable state at the onset of ten consecutive severely errored seconds. In this
state, the receive framer inhibits incrementing of the severely errored and errored second counters for the dura-
tion of the unavailable state. The receive framer deasserts the unavailable state condition at the onset of ten
consecutive errored seconds which were not severely errored.
11.The
4-bit Sa6 codes
(FRM_SR2 bit 3—bit 7).
Sa6 codes are asserted if three consecutive 4-bit patterns have been detected. The alarms are disabled when
three consecutive 4-bit Sa6 codes have been detected that are different from the pattern previously detected.
The receive framer monitors the Sa6 bits for special codes described in ETS Draft prETS 300 233:1992 Sec-
tion 9.2. The Sa6 codes are defined in Table 41 and Table 42. The Sa6 codes in Table 41 may be recognized as
an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as the receive framer is in the basic
frame alignment state. In the CRC-4 mode, the receive framer can optionally recognize the received Sa6 codes
in Table 41 synchronously to the CRC-4 submultiframe structure as long as the receive framer is in the CRC-4
multiframe alignment state (synchronous Sa6 monitoring can be enabled by setting register FRM_PR10 bit 1 to
1). The Sa6 codes in Table 42 are only recognized synchronously to the CRC-4 submultiframe and when the
receive framer is in CRC-4 multiframe alignment. The detection of three (3) consecutive 4-bit patterns are
required to indicate a valid received Sa6 code. The detection of Sa6 codes is indicated in status register
FRM_SR2 bit 3—bit 7. Once set, any three-nibble (12-bit) interval that contains any other Sa6 code will clear
the current Sa6 status bit. Interrupts may be generated by the Sa6 codes given in Table 41.
Table 41. Sa6 Bit Coding Recognized by the Receive Framer
Code
First Receive Bit (MSB)
Last Received Bit (LSB)
Sa6_8
hex
Sa6_A
hex
Sa6_C
hex
Sa6_E
hex
Sa6_F
hex
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
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