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參數(shù)資料
| 型號(hào)： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁(yè)數(shù)： | 36/248頁(yè) |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
26
Lucent Technologies Inc.
Line Interface Unit: Block Diagram
The T7633 LIU diagram is shown in Figure 5. Only a single transceiver is shown here for illustration purposes.
5-4556(F).cr.4
* INTSYSCK always runs at 16 times the primary line rate. If CKSEL = 1, INTSYSCK is equal to SYSCK. If CKSEL = 0, INTSYSCK is sourced
from the internal 16x clock multiplier.
Figure 5. Block Diagram of Line Interface Unit: Single Channel
Line Interface Unit: Receive
Data Recovery
The receive line-interface unit (RLIU) transmission format is bipolar alternate mark inversion (AMI). The RLIU
accepts input data with a data rate tolerance of
±
130 ppm (DS1) or
±
80 ppm (E1). The RLIU first restores the
incoming data and detects analog loss of signal. Subsequent processing is optional and depends on the program-
mable LIU configuration established within the microprocessor interface registers. The RLIU utilizes an equalizer to
operate on line length with typically up to 15 dB of loss at 772 kHz (DS1) or 13 dB loss at 1.024 MHz (E1). The sig-
nal is then peak-detected and sliced to produce digital representations of the data. Selectable digital loss of signal,
jitter attenuation, and data decoding are performed.
The clock is recovered by a digital phase-locked loop that uses SYSCK as a reference to lock to the data rate com-
ponent. Because the reference clock is a multiple of the received data rate, the internal RLCK (RLCK-LIU) output
will always be a valid DS1/CEPT clock that eliminates false lock conditions. During periods with no receive input
signal from the line, the free-run frequency of RLCK-LIU is defined to be either SYSCK/16 or SYSCK depending on
the state of CKSEL. RLCK-LIU is always active with a duty cycle centered at 50%, deviating by no more than
±
5%.
Valid data is recovered within the first few bit periods after the application of SYSCK.
INTSYSCK
*
TO RECEIVE
FRAMER
FROM TRANSMIT
FRAMER
RTIP
RRING
FLLOOP
(NO LIU AIS)
EQUALIZER
SLICERS
CLOCK AND
DATA
RECOVERY
RDLOS
RND_BPV
RPD
RLCK
DECODER
DLLOOP
RLOOP
TLCK-LIU
TND-LIU
JITTER
ATTENUATOR
(RECEIVE PATH)
TPD-LIU
(DUFLLOOP
PULSE-
WIDTH
CONTROLLER
TDM
LOTC
EPULSE
TRANSMIT
DRIVER
TTIP
TRING
SYSCK
LOSS OF
SYSCK
MONITOR
DIVIDE BY 16
ALARM
INDICATION
SIGNAL (AIS)
ENCODER
RALOS
JITTER
ATTENUATOR
(TRANSMIT PATH)
(CLOCK)
(DATA)
LOSS
OF
TLCK
16x
CLOCK
MULTIPLIER
CKSEL
INTSYSCK
*
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