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參數(shù)資料
| 型號： | T7633 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 3.3 V Short-Haul Terminator(雙T1/E1 3.3V短通信距離終端器) |
| 中文描述： | 雙T1/E1的3.3伏短途終結(jié)者（雙T1/E1的3.3短通信距離終端器） |
| 文件頁數(shù)： | 126/248頁 |
| 文件大?。?/td> | 1459K |
| 代理商： | T7633 |
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Advance Data Sheet
T7633 Dual T1/E1 3.3 V Short-Haul Terminator
May 1998
116
Lucent Technologies Inc.
Facility Data Link (FDL)
(continued)
HDLC Operation
(continued)
Flags
1
All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automatically
sends two flags between frames. If the chip-configuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the 1s
idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC
block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive
frames with a shared flag; therefore, two successive flags will not share the intermediate 0.
An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO
and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is
read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data
byte with the CRC sequence and a closing flag.
The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are
recognized as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As
mentioned above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and deletion. The
HDLC receiver recognizes a single flag between frames as both a closing and opening flag.
1.Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two
flags.
Aborts
An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register
FDL_PR3 bit 6 (FTABT). This causes the last byte written to the transmit FIFO to be replaced with the abort
sequence upon transmission. Once a byte is tagged by a write to FTABT, it cannot be cleared by subsequent writes
to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC
should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a
transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy
way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the
queue.
When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven
consecutive 1s. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame
alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the
status of frame status byte (see Table 54, Receive Status of Frame Byte, on page 112) which is appended to the
receive data queue. All subsequent bytes are ignored until a valid opening flag is received.
Idles
In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received 1s as idle.
When the HDLC block receives 15 contiguous 1s, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set.
For transmission, the 1s idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS control bit in
register FDL_PR0 bit 1 is 0, the 1s idle byte is sent as the time-fill byte between frames. A time-fill byte is sent when
the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames are sent
back-to-back otherwise.
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