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參數(shù)資料
| 型號(hào)： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 426K |
| 代理商： | STLC1510 |
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STLC1510
8.4 AFE Interface
The interface to the companion Analog Front-end de-
vice (STLC1511) operates at a rate of 35.328MHz. It
consists of two types:
I
A serial signal interface for transferring DAC
and ADC samples to and from the Aloha ASIC
ASIC.
I
A serial control interface for Aloha ASIC.
The serial signal interface to the Aloha ASIC provides
for transport of transmit and receive data between
the LAVA ASIC and Aloha ASIC. This is accom-
plished with a two bit wide data stream in each direc-
tion plus the appropriate clocks. Refer to Figure 27.
for the timing diagram of this interface.
The serial signal interface consists of six pins:
I
A 35.328MHz continuous clock output
(
CK35M
);
I
A dual serial pin input pin for ADC samples
(
RxSIN
);
It can carry up to 16 bits. The exact
number of bits carried is programmable
between 12 and 16. Refer to the AFE
interface definition for details.
I
A dual serial pin output pin for DAC samples
(
TxSOUT
);
I
It can carry up to 16 bits. The exact number of
bits carried is programmable between 14 and
16. Refer to the AFE interface definition for
details
I
An ADC and DAC sample clock input
(
A_SCLK
).
I
ForTX and RXinterface, data is senton positive
edge of clock and sampled by the receiver on
the negative edge of the clock.
The serial control I/F consists of 4 pins:
I
SPI_CLK: a gated 35.328MHz clock.It is only
present during digital I/Fread/write cyclesand is
inactive otherwise.
I
SPI_ENB: an active lowenable pinwhich allows
selection between different AFEs if required.
I
SPI_DTX: an output data pin which is used to
send control information to the AFE ASIC.
I
SPI_DRX: an input data pin which is used
receive control information from the AFE ASIC.
It is enabled only whenR/Wis low.
The format for the serial interface is given below:
I
R/W- determines the access mode for the
register address[b1:b0]
I
ADDR[b2:b0]- identifies the control register
accessed. These registers will correspond to
the mapping in the LAVA ASIC.
I
WR_DATA[b7:b0]- the control data written to
the AFE ASIC.
Figure 27. AFE ADC/DAC Sample Serial Interface Timing Diagram
C K35M
TxS O UT[0]
TxS O UT[1]
a 7
a 15
a6
a1 4
a 5
a 13
a 4
a 12
a 3
a 11
a2
a1 0
a 1
a 9
a0
a8
A _SC LK
b 7
b 15
b 6
b 14
b 5
b1 3
b 4
b 12
b3
b 11
b 2
b10
b 1
b9
R xS IN[0]
R xSIN[1]
b 0
b8
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