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參數(shù)資料
| 型號： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 12/40頁 |
| 文件大小： | 426K |
| 代理商： | STLC1510 |
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STLC1510
12/40
Figure 3. NIF Off-Chip Signals
The following tasks are performed by the ATM net-
work (in accordance with ITU-T Recommendation
I.432.1), and therefore do not have to be implement-
ed in the STLC1510 when using the CDIF:
I
HCS generation (Tx).
I
Payload scrambling (Tx).
I
Optionally, enables clear channel mode, in
which HCS generation and payload scrambling
are disabled (Tx).
I
HCS cell delineation (Rx).
I
Payload descrambling (Rx).
I
Idle cell filtering (Rx).
I
Header error detection to recover valid ATM
cells (header correction is not implemented)
(Rx).
I
Optionally, enables clear channel mode, in
which every 53 x 8 = 424 bits are collected by
the receiver and sent to the backplane (Rx).
5.1.4 UTOPIA Level 2 Interface and Controller
The Universal Test and Operations Physical Inter-
face for ATM (UTOPIA) provides a standard that links
ATM layer or various management entities with a va-
riety of physical (PHY) layers.
The UTOPIA IF has the following features:
I
provides clock decoupling mechanism.
I
throttles data flow from the ATM layer.
I
indicates to the ATM layer when the modem is
ready to receive data.
I
signals to the ATM layer the presence of valid
data for transmission.
I
Recognizes the address when the modem is
selected for communication.
I
Supports octet-level and/or cell-level
handshaking.
I
UTOPIA Level 2 supports a multi-PHY
operation for up to n PHY devices where,
I
n=< 8 at ATM layers intended for 155 Mbps;
U2PHY
RX
URxData[7:1]
RxEnb
RxSOC
RxAddr[4:0]
8
5
CDIF
RX
URxData[0]
RxClk
U2PHY
TX
UTxData[7:1]
TxEnb
TxSOC
TxAddr[4:0]
TxClav
8
5
CDIF
TX
UTxData[0]
TxClk
RxParity
TxParity
TxBP
RxClav
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