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參數(shù)資料
| 型號： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 426K |
| 代理商： | STLC1510 |
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STLC1510
16/40
5.5.1 EPM Attributes
I
It provides access to internal registers for
control and monitoring of the various hardware
blocks.
I
Provides control to perform Software (SW)
download into the EPM and BPU memories as
part of the power up sequence.
I
Provides interrupt and exception handling for
various macro blocks.
I
Software on the EPM preforms several DSP
functions that are not implemented in the BPU
during Start-up, fast re-train or Show Time.
I
Address space is large enough to address the
internal registers, on-chip and some off-chip
memories
I
Provides debugging access through a JTAG
interface, for SW running on the processor.
I
Provides a dual port RAM to pass messages
between the D950 and ARM7 cores.
I
Supports an external Host Processor Interface
to pass messages to/from the ARM7
I
Both cores have embedded emulator blocks for
debug
5.5.2 ARM7TDMI MCU Core
The ARM7TDMI is a member of the Advanced RISC
Machines (ARM) family of general purpose 32-bit mi-
croprocessors. The architecture is based on the Re-
duced Instruction Set Computer (RISC) principle
which results in high instruction throughput and fast
real-time interrupt response.
Pipelining is employed so that all parts of the pro-
cessing and memory systems can operate continu-
ously. While one instruction is being executed, the
next is being decoded while the next is being fetched
from memory.
Attributes:
I
32-bit register bank
I
32-bit ALU
I
32-bit shifter
I
32-bit addressing
I
32x8 DSP multiplier
I
”Thumb” architectural extension which allows
generation of more memory efficient code
I
Peripherals include decoders, timer and
interrupt controller
5.6 D950 DSP Core
The D950 core is a 16-bit DSP based on the Harvard
architecture with three bidirectional 16-bit buses, two
for data and one for instruction. Each of these buses
is dedicated to a unidirectional 16-bit address bus
(XA/YA/IA).
The core is composed of three main units, a Data
Calculation Unit (DCU), an Address Calculation Unit
(ACU) and a Program Control Unit (PCU).
Attributes
I
Data Calculation Unit
I
Address Calculation Unit
I
Program Control Unit
I
16x16 single cycle MAC
I
fast and flexible buses
The D950 top level consists of a D950 core, I mem,
X mem1 (8 bit), X mem2 (16 bit), Y mem, Timer, Em-
ulator, Interrupt Controller and TAP peripherals.
5.6.1 BAD - Bridge, Arbiter, Decoder
The Bridge/Arbiter/Decoder (BAD) block controls the
data traffic among the ARM7, the D950 and the data
pump. It provides decoding circuitry, LAMBA bus ar-
bitration and isolation buffers.
5.6.2 DPCOMM - Dual Port RAM Messaging
between ARM and D950
A Dual Port SRAM (1024x16) plus control registers,
is connected between the APB bus of the ARM7 and
the X bus of the D950. It is used as a mailbox to pass
data between the ARM and the D950 DSP.
5.7 Host Processor Interface (HPI)
I
The HPI resides on the APB bus of the ARM7.
The chip select for the HPI is generated by the
APB Bridge. Since the HPI resides on the APB,
it is treated as a 16 bit entity. This means that
APB Address 0isignored and allHPIaddresses
are on 16 bit boundaries. i.e. incremental
address location are h0000 h0002 h0004 etc...
I
The HPI is dual port SRAM based with control
that generates an interrupt when a message
wants to be passed. The DPSRAM is
implemented on-chip.
I
External to the ASIC, the pins of this interface
are 8 bidirectional data pins, 3 input address
pins, 1 inputRead/Writen pin,1 Address Strobe,
1 clock, 1 input chip select pin and 1 output
interrupt pin.
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