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參數(shù)資料
| 型號： | STLC1510 |
| 廠商： | 意法半導體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 17/40頁 |
| 文件大小： | 426K |
| 代理商： | STLC1510 |
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STLC1510
I
A status register, an index register (for the Host
Processor), an interrupt mask register, and a
message buffer are required for both input and
output transactions.
I
The Input Status Register (ISR) is set by the
Host Processor by writing h01 and cleared by
writing h00 to the location. It is cleared by ARM
by writing anything to it.
I
The OutputStatus Registers (OSR) isset by the
ARM by writing h01 and cleared by writing h00.
It is cleared by the Host Processor by writing
anything to it.
I
The Input and Output Index Registers (IIR &
OIR respectively) are reset to their starting
value by writing h00 to their respective
addresses. They can also be cleared by the
Host Processor by writing anything to them.
I
The InputInterrupt Mask Register(IIM) resets to
h00, causing the Mask to be set (active low).
This means that before the ARM can receive
message ready interrupts from the Host
Processor, this register must be written with
h0001 (by ARM) to unmask the interrupt.
I
The Output Interrupt Mask Register (OIM)
resets toh00, causing theMask to beset (active
low).This meansthatbefore theHostProcessor
can receive message ready interrupts from the
ARM, this register must be written with h01 (by
the Host Processor) to unmask the interrupt.
I
The Inputand OutputMessage buffers are each
256 bytes long and 1 byte wide (an overflow in
the index register will not write to the other
message buffer, but will start to overwrite the
current message buffer).
I
Addressing of the Input and Output Message
Buffers by the Host Processor is implemented
indirectly via the Input and Output Index
Registers.
I
An external interrupt signal is generated when
the output status register isset by theARM7. An
ARM7 interrupt signal is generated when the
input status register is set by the Host
Processor.
Figure 5. HPI Block Diagram
256 Bytes
Input Message
Buffer
HPI_CSN
HPI_RWN
HPI_ADDR[2:0]
HPI_DATA_IN[7:0]
HPI
S
L
A
V
E
A
P
B
ARM2HP_INT
HPI2ARM_INT
C
N
T
R
L
H
P
PSEL_HPI
PWRITE
PENABLE
PADDR[10:1]
PD_W[7:0]
Output Index Reg
Input Status Reg
Input Index Reg
Input Int Mask
256 Bytes
Output
Message
Buffer
Read/Write
Read
Read
Read/Write
Output Status Reg
Output Int Mask
HPI_ASN
BRESn
HPI_DATA_OUT[7:0]
HPI_DATA_OEN
BCLK
HPI_CLK
PD_R[15:0]
To/From
ARM
To/From
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