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參數(shù)資料
| 型號： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 426K |
| 代理商： | STLC1510 |
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STLC1510
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n=< 4 at ATM layers intended for 622 Mbps.
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This interface is subdivided into two parts: the
Transmit Interface (TxIF) and the Receive
Interface (RxIF).
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Both the TxIF and RxIF are controlled by the
ATM layer.
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The ATMlayerprovides an interface clock tothe
PHY layer for synchronizing all interface
transfers.
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The PHY layer will incorporate rate-matching
buffers.
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Transmit data is transferred from the ATM layer
to the PHY layer as follows: first, the PHY layer
indicates it can accept data, then the ATM layer
drives data onto the data bus and asserts the
TxEnb.
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The data flow is controlled by the PHY layer.
For a complete definition of TxIF signals and RxIF
signals please consult the UTOPIA Level 1 and UTO-
PIA Level 2 documents released by The ATM Forum
Technical Committee.
There is an additional signal added to the Utopia In-
terface in the TX direction: Back Pressure (TxBP).
This signal alerts the backplane when a software pro-
grammable depth has been reached in the TX Utopia
FIFO, while still allowing more data (up to the 10 cells
maximum) to be accepted by the FIFO.
5.1.5 ATM Transport Convergence (TC) Layer
Processor
The Cell TC block has the following attributes:
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Idle cells inserted in the Tx direction for cell rate
de-coupling are discarded.
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HEC bytes are generated in the Tx direction as
described in ITU-T Recommendation I.432,
including the recommended modulo-2 addition
(XOR) of the pattern binary 01010101 to the
HEC bits.
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Scrambling of the cell payload is used in the
transmit direction to improve the security and
robustness of the HEC cell delineation
mechanism. The cellpayload isdescrambled by
the Cell TC block of an ATU receiver.
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When interfacing ATM bytes to the bearer
channel, the most significant bit (msb) is sent
first.
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Cell delineation is performed using a coding law
checking the HEC field in the cell header
according to the algorithm described in ITU-T
Recommendation I.432.
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Error detection is performed asdefined in ITU-T
Recommendation I.432 with the exception that
any HEC error is considered a multiple-bit error.
Therefore, HEC error correction is not
performed.
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The ATU-C transmitter preserves V-C and T-R
interface byte boundaries (explicitly present or
implied by ATM cell boundaries) at the U-C
interface.
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Interfaces to the Lamba bus.
5.2 FIFO
The STLC1510 incorporates 4 FIFO buffers for rate
decoupling:
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Utopia TX FIFO (8 bit input from the Utopia TX
interface, 16 bit output to the ATM-TC cell
processor): 243 words X 16 bits/word = 486
bytes >= 9 ATM cells @ 53 bytes/cell
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Utopia RX FIFO (16 bit input from the ATM-TC
cell processor, 8 bit output to the Utopia RX
interface): 54 words X 16 bits/word = 108 bytes
>= 2 ATM cells @ 53 bytes/cell
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Lamba TX FIFO (16 bit input from the ATM-TC
cell processor, 8 bit output to the Lamba Bus):
106 words X 16 bits/word = 212 bytes >= 4 ATM
cells @ 53 bytes/cell
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Lamba RX FIFO (8 bit input from the Lamba
Bus, 16 bit output to the ATM-TC cell
processor): 106 words X 16 bits/word = 212
bytes >= 4 ATM cells @ 53 bytes/cell
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All the FIFO’s share the following features:
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Perform 8-bit to 16-bit word conversion or 16-bit
to 8-bit word conversion, with storage
implemented as 16-bit wide dual port RAMs.
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Flags indicating when the FIFO is full, almost
full, empty, almost empty and half empty. (The
FIFO depths for the almost full and almost
empty flags are hard-wired).
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Diagnostic input and an error flag.
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The Utopia Tx FIFOhas the following additional
attributes:
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