參數資料
型號: STLC1510
廠商: 意法半導體
英文描述: NorthenLite G.lite DMT Transceiver
中文描述: NorthenLite G.lite大唐收發(fā)器
文件頁數: 34/40頁
文件大小: 426K
代理商: STLC1510
STLC1510
34/40
Forum Technical Committee’s Utopia Level 1
and Utopia Level 2 specifications, and Chapter
7 of this document, Network Interface and
Controller (NIF).
Features of MPHY Layer Cell-Level Handshake (Tx
Direction):
I
A single MPHY port at a time is selected for a
cell transmission. However, another MPHY port
may be polled for its TxClav status while the
selected MPHY port transfers data. The ATM
layer polls the TxClav status of a MPHY port by
placing its address on TxAddr. The MPHY port
(STLC1510 device) drives TxClav during each
cycle following one with its address on the
TxAddr lines.
I
The ATM layer selects a MPHY port for transfer
by placing the desired MPHY address onto
TxAddr, when TxEnb is deasserted (high)
during the current clock cycle, and asserted
(low) during the next clock cycle. All MPHY
devices only examine the value on TxAddr for
selection purposes when TxEnb is deasserted
(high). The MPHY port is selected starting from
the cycle afteritsaddress ison the TxAddrlines,
and TxEnb is deasserted (high); and ending in
the cycle a new MPHY port is addressed for
selection, and TxEnb is deasserted (high).
Figure 23. depicts the polling phase and the selection
phase of the UTOPIA2 transmit interface. After the
selection of the MPHY port, the cell transfer is exe-
cuted the same way as in UTOPIA Level 1.
Figure 23. UTOPIA Level 2 transmit timing, polling phase and selection phase.
TxClk
TxEnb
UTxData
TxClav
TxSOC
N-1
P40
P41
P42
P43
P44
P 45
P46
P47
P48
H1
H 2
H3
H4
1F
1F
1F
1F
1F
1F
1F
N+1
N+3
N
N +1
N+3
N -1
N-1
N+3
N+1
N
N +3
N+1
TxAddr
PHY N
PHY N+3
polling
polling
Cell transmission to:
selection
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