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參數(shù)資料
| 型號(hào)： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 426K |
| 代理商： | STLC1510 |
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STLC1510
18/40
5.7.1 Send Message from Host Processor to
ARM
I
Read Input Status Register. Ifh01, the ARM has
not read out the last message. If h00, the ARM
has read the last message and the Input
Message Buffer is available for use.
I
Clear Input Index Reg by writing any value to its
address (b’100).
I
Write message into Input Message Buffer by
consecutively writing to its address (b’111). Each
write will cause the Input Index Register to
increment by 1 and access another byte location.
I
Write h01 to Input Status Register (address
b’011) to interrupt the ARM
5.7.2 Receive Message from ARM by Host
Processor
After receiving interrupt from ARM:
I
Clear Output Index Register (address b’001) by
writing any value.
I
Read message from Output Message Buffer by
consecutively reading from its address (b’110).
Each read will cause the Output Index Register to
increment by 1 and access another byte location.
I
Clear theOutput Status Reg (address b’000) by
writing any value (the ARM can clear the OSR
by writing 0 to it).
I
Send Message from ARM to Host Processor
I
Read Output Status Register. If h0001, the HP
has not read out the last message. If h0000, the
HP has read the last message and the Output
Message Buffer is available for use.
I
Write message into Output Message Buffer.
This buffer is directly addressable by the ARM.
I
Write h0001 to Output Status Register to
interrupt the HP
5.7.3 Receive Message from Host Processor
by ARM
After receiving interrupt from HP:
I
Read message from Input Message Buffer.This
buffer is directly addressable by the ARM.
I
Clear the Input Status Reg by writing h0001 to its
address (the HP can clear the ISR by writing 0 to it).
Table 3. Signal List
Name
I/O
Internal/
External
I/F
Description
BRESn
I
Internal
APB
Active low master RESET
BCLK
I
Internal
APB
ASB clock
PSEL_HPI
I
Internal
APB
Active high block select from APB
PADDR[10:1]
I
Internal
APB
APB address [11:1]
PD_W[7:0]
I
Internal
APB
APB write data
PD_R[15:0]
O
Internal
APB
APB read data
PWRITE
I
Internal
APB
APB Write - Active high, Read - Active low
PENABLE
I
Internal
APB
APB enable signal for timing
HP2ARM_INT
O
Internal
APB
Interrupt from Host Processor to ARM
HPI_CLK
I
External
HP
Host Processor bus clock
HPI_CSN
I
External
HP
Active low select from Host Processor
HPI_ASN
I
External
HP
Address Strobe from Host Processor
HPI_RWN
I
External
HP
HP Read - Active high, Write - Active low
HPI_ADDR[2:0]
I
External
HP
Host Processor address
HPI_DATA_IN [7:0]
I
External
HP
Host Processor data in
HPI_DATA_OUT [7:0]
O
External
HP
Host Processor data out
HPI_DATA_OEN
O
External
HP
Host Processor data output enable
ARM2HP_INT
O
External
HP
Interrupt from ARM to Host Processor
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