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參數(shù)資料
| 型號(hào)： | STLC1510 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NorthenLite G.lite DMT Transceiver |
| 中文描述： | NorthenLite G.lite大唐收發(fā)器 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大小： | 426K |
| 代理商： | STLC1510 |
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STLC1510
22/40
5.11.1DFT Interfaces
The STLC1510 incorporates certain features (Design
for Testability, DFT) to improve the coverage of the fi-
nal production test. Certain pins are dedicated to this
features, and should not be used during normal oper-
ation. The Test Interface pins need to be connected
as follows:
5.11.2General Purpose I/O (GPIO) Interface
The STLC1510 has a 8-bit General Purpose I/O port
Figure 8. GPIO Interface Block Diagram
to allow low speed control and monitoring of external
signals via the LAMBA bus. The block diagram for
this interface is shown in Figure 8.
The GPIO has the following attributes:
I
There are 8 GPIO pins.
I
Each pin can be individually set to one of 4
modes:
Input mode: Input signals will be sam-
pled with LAMBA bus clock and stored in
GPIO_in
register.
Output mode: The GPIO pin is driven
with the state in the
GPIO_out
register.
Interrupt mode: The
GPIO_int
register
is set when there is a negative transition
detected on its corresponding GPIO pin.
The logic levelof each interrupt pin will as
well be stored in the
GPIO_in
register. An
interrupt condition on any of the GPIO
pins will result in an interrupt to the D950.
Dedicated mode. The GPIO pin is con-
figured to be its second function accord-
ing to the Table below If the pin does not
have a second function, it will be config-
ured as an input pin.
I
There isno external clockfor the GPIOinterface
and as such no timing defined.
Signal
BGA
Connected to
TCK
N9
Pull-Up
TMS
N7
Pull-Up
TDI
P8
Pull-Up
TDO
N8
open
TRSTN
P9
See “RESET Structure” on
page 21.
Lam ba Bus Interface (LBI)
Lam ba
Bus
GPIO_in
GPIO_out
GPIO_int
G
GPIO[7:0]
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