參數資料
型號： SPAK302FC25C
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
封裝： 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132
文件頁數： 84/128頁
文件大小： 641K
代理商： SPAK302FC25C
ETHERNET Controller
4-20
MC68EN302 REFERENCE MANUAL
MOTOROLA
The transmit FIFO control logic provides a signal indicating data is available to the Ethernet
transmit protocol machine. If underflow occurs, the Ethernet transmit protocol machine will
handle aborting the frame (append a bad CRC) and flushing the remainder of the frame from
the FIFO.
If a collision occurs within the slot time in a transmit frame, the FIFO supports retry by
maintaining a separate start of frame pointer (read lag pointer). New data is never written on
top of start of frame data until the slot time has passed. Two control signals pass between
the Ethernet transmit logic and the transmit FIFO to indicate when the slot time (collision
window) has been passed (Transmit Accept) or when a collision retry must take place
(Transmit Retry).
4.4.2 RECEIVE FIFO
The receive FIFO control logic provides “data available” and “receive FIFO empty” flow
control signals to the receive DMA controller. The “data available” signal is asserted as a
function of the number of bytes available in the FIFO and the WMRK bits from the EDMA
register. If overflow occurs, the STATUS word will have the OU bit set which will be written
into the receive BD. The frame should be discarded by software.
Data is written into the receive FIFO by the Ethernet receive logic in the case of status
information, and by the address recognition logic if the Reason and ARIndex fields are
enabled.
The receive FIFO control logic maintains a “start of frame” pointer that allows purging
collision fragments from the FIFO so that they need not be DMA’d. This purging of fragments
(runt frames less than 64 bytes long) is automatic and cannot be disabled.
4.5 ETHERNET PROTOCOL LOGIC
This block implements the MAC (media access control) sublayer of the IEEE 802.3
standard, supporting operation up to 10 Mbps compliant with both Ethernet and 802.3
standards. This logic is subdivided into transmit, receive and loopback/serial interface
sections.
4.5.1 ETHERNET TRANSMIT
The Ethernet transmiter block performs the following functions:
Parallel to serial conversion of data
Encapsulation of transmit frames
— Generation of preamble (PA) and start of frame delimiter (SFD)
— Transmits serial data from the transmit FIFO interface
— Pads short frames (with 0’s)
— Appends CRC, if required
— Appends bad CRC if required
— Appends JAM pattern (all 1’s)
Transmit Protocol
相關PDF資料
PDF描述
MC68EN360EM25 7 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
MC68EN360FE33 RISC MICROCONTROLLER, CQFP240
MC68360RC25 RISC MICROCONTROLLER, CPGA241
MC68EN360RC25 RISC MICROCONTROLLER, CPGA241
MC68360FE25 32-BIT, 25 MHz, RISC PROCESSOR, CQFP240
相關代理商/技術參數
參數描述
SPAK56854FG120 制造商:Freescale Semiconductor 功能描述:
SPAK56857BU120 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:120 MIPS Hybrid Processor
SPAK56F803BU80 制造商:Freescale Semiconductor 功能描述:
SPAK56F805FV80 制造商:Freescale Semiconductor 功能描述:
SPAKDSP303AG100 功能描述:數字信號處理器和控制器 - DSP, DSC SPAKDSP303AG100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*