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參數(shù)資料
| 型號： | SPAK302FC25C |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| 封裝： | 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 |
| 文件頁數(shù)： | 127/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | SPAK302FC25C |
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IEEE 1149.1 (JTAG) Test Access Port
MOTOROLA
7-13
7.4.1 EXTEST
The external test (EXTEST) instruction selects the 163-bit boundary scan register.
By using the TAP, the register is capable of a) scanning user-defined values into the output
buffers, b) capturing values presented to input pins, c) controlling the direction of bidirec-
tional pins, and d) controlling the output drive of three-stateable output pins. For more details
on the function and use of EXTEST, refer to the IEEE 1149.1 document.
7.4.2 SAMPLE/PRELOAD
The SAMPLE/PRELOAD instruction provides two separate functions. First, it provides a
means to obtain a snapshot of system data and control signals. The snapshot occurs on the
rising edge of TCK in the capture-DR controller state. The data can be observed by shifting
it transparently through the boundary scan register.
NOTE
Since there is no internal synchronization between the scan
chain clock (TCK) and the system clock (CLKO), the user must
provide some form of external synchronization to achieve mean-
ingful results.
The second function of SAMPLE/PRELOAD is to initialize the boundary scan register output
cells prior to selection of EXTEST. This initialization ensures that known data will appear on
the outputs when entering the EXTEST instruction.
7.4.3 BYPASS
The BYPASS instruction selects the single-bit bypass register as shown in Figure 7-11. This
creates a shift register path from TDI to the bypass register and, finally, to TDO, circumvent-
ing the 163-bit boundary scan register. This instruction is used to enhance test efficiency
when a component other than the MC68EN302 becomes the device under test.
Figure 7-11. Bypass Register
When the bypass register is selected by the current instruction, the shift register stage is set
to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the
first bit to be shifted out after selecting the bypass register will always be a logic zero.
1
Mux
G1
C
D
TO TDO
FROM TDI
0
SHIFT DR
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| SPAKDSP303AG100 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC SPAKDSP303AG100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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