參數(shù)資料
型號(hào)： SN54LVT8980JT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁(yè)數(shù)： 8/36頁(yè)
文件大?。?/td> 509K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
counter register
The counter register, while only 8 bits wide like any other eTBC register, provides read/write access to the full
32-bit eTBC counter. Writes to the counter register are accomplished by four complete host access cycles,
otherwise the counter is considered unloaded (CTRS = 0). Reads to the counter register likewise are
accomplished by four complete host access cycles. However, reads do not affect the counter-loaded status
(CTRS). The counter access (both read and write) is in least-significant-byte-first order. Any writes to the counter
register while a command is in progress are ignored. The 32-bit value present in the counter at initiation of a
command is used to determine the number of TCK cycles or scan bits for which the command is operated.
TDO-buffer register
The TDO-buffer register, while only 8 bits wide like any other eTBC register, provides write access to the full
4
× 8 (32-bit) FIFO that comprises the TDO buffer. The TDO-buffer register can be written as long as the TDO
buffer does not become full. When the TDO buffer becomes full, further writes to the TDO-buffer register cause
RDY inactive (and consequent hold or wait states to be sent back to the host, if supported) and cause the write
to be ignored if the write cycle is terminated before the TDO-buffer-full status is cleared.
TDI-buffer register
The TDI-buffer register, while only 8 bits wide like any other eTBC register, provides read access to the full 4
× 8
(32-bit) FIFO that comprises the TDI buffer. The TDI-buffer register can be read as long as the TDI buffer does
not become empty. When the TDI buffer becomes empty, further reads to the TDI-buffer register cause RDY
inactive (and consequent hold or wait states to be sent back to the host, if supported) and cause the read data
to be invalid if the read cycle is terminated before the TDI-buffer-empty status is cleared.
discrete-control register
The discrete-control register is used to program the state of the TAP outputs (TCK, TDO, TMS, TRST) and to
poll the state of the TAP input (TDI) when the eTBC is in its discrete-control mode. The contents of the
discrete-control register determine values output to TDO, TMS, and TRST according to the decode in Table 6.
The TCK output is generated on each read and write to the discrete-control register; writes generate TCK falling
edge, while reads generate TCK rising edge. In modes other than the discrete-control mode, this register is fully
writeable and readable, but writes and reads have no effect on eTBC or target operation.
Table 6. Discrete-Control Register Decode
DISCRETE CONTROL
VALUE
RESULT
BIT GROUP
BIT NO.
VALUE
RESULT
DNTR
3
0
If in discrete-control mode, output low to TRST pin, otherwise nothing
DNTR
3
1
If in discrete-control mode, output high to TRST pin, otherwise nothing
DTMS
2
0
If in discrete-control mode, output low to TMS pin, otherwise nothing
DTMS
2
1
If in discrete-control mode, output high to TMS pin, otherwise nothing
DTDI
1
0
The TDI data received is a logic 0.
DTDI
1
The TDI data received is a logic 1.
DTDO
0
If in discrete-control mode, output low to TDO pin, otherwise nothing
DTDO
0
1
If in discrete-control mode, output high to TDO pin, otherwise nothing
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