參數(shù)資料
型號： SN54LVT8980JT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁數(shù)： 6/36頁
文件大?。?/td> 509K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
status register
The status of the eTBC is fully reported and continuously updated in the status register. The decode of the
various bit groups assigned to the status register is given in Table 4.
Table 4. Status Register Decode
STATUS
BIT
GROUP
BIT NO.
VALUE
RESULT
TDIS
7
0
The TDI buffer is empty – no TDI data is available for host read.
TDIS
7
1
The TDI buffer is not empty – at least one byte of TDI data is available for host read.
TDOS
6
0
The TDO buffer is not full – at least one byte in TDO buffer is available for host write.
TDOS
6
1
The TDO buffer is full – no bytes in TDO buffer are available for host write.
CTRS
5
0
The counter is not loaded with a complete 32-bit value – command operation cannot begin until counter
load completes.
1
The counter is loaded with a complete 32-bit value – command operation can begin.
0000
The current target TAP state (as sent by eTBC) is Test-Logic-Reset.
0001
The current target TAP state (as sent by eTBC) is Select-DR-Scan.
0010
The current target TAP state (as sent by eTBC) is Capture-DR.
0011
The current target TAP state (as sent by eTBC) is Shift-DR.
0100
The current target TAP state (as sent by eTBC) is Exit1-DR.
0101
The current target TAP state (as sent by eTBC) is Pause-DR.
0110
The current target TAP state (as sent by eTBC) is Exit2-DR.
TAPST
3 0
0111
The current target TAP state (as sent by eTBC) is Update-DR.
TAPST
3–0
1000
The current target TAP state (as sent by eTBC) is Run-Test/Idle.
1001
The current target TAP state (as sent by eTBC) is Select-IR-Scan.
1010
The current target TAP state (as sent by eTBC) is Capture-IR.
1011
The current target TAP state (as sent by eTBC) is Shift-IR
1100
The current target TAP state (as sent by eTBC) is Exit1-IR.
1101
The current target TAP state (as sent by eTBC) is Pause-IR.
1110
The current target TAP state (as sent by eTBC) is Exit2-IR.
1111
The current target TAP state (as sent by eTBC) is Update-IR.
The TDI-buffer-status (TDIS) bit reports the readiness of the TDI buffer to respond to a host read. The
TDO-buffer-status (TDOS) bit reports the readiness of the TDO buffer to respond to a host write. The
counter-status (CTRS) bit reports the readiness of the counter to support a command that uses the counter. The
current-TAP-state (TAPST) bit group continuously reports the target TAP state as monitored by the eTBC.
command register
The command register is used to perform software reset of the eTBC, to discretely control the state of the TRST
output when not in discrete-control mode, and to initiate test operations in the target(s).The decode of the
various bits assigned to the command register is given in Table 5.
Any read to the command register while a command is in progress returns the value written to the command
register upon initiation of the command. Once a command finishes, the operation-code (OPCOD) bit group in
the command register is reset to null. In this way, the status of a requested command can be monitored/polled
by the host.
With the exception of the software-reset (SWRST) bit, which can be written at any time, writes to the command
register while a command is in progress causes RDY inactive and is ignored if the write cycle is terminated
before the previously requested command finishes.
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