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參數(shù)資料
| 型號(hào)： | SN54LVT8980JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 509K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
4 V
500
500
Data Input
Timing Input
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPLH
VOH
VOL
2.7 V
0 V
Input
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
2 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
4 V
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50 , tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Open
1.5 V
Figure 9. Load Circuit and Voltage Waveforms (D and RDY Outputs)
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