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參數(shù)資料
| 型號： | SN54LVT8980JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 509K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
instruction-register scan commands
The instruction-register scan commands scan bits to and/or from the concatenation of instruction registers in
a target scan chain. The eTBC generates a TMS sequence to move the target scan chain from its current TAP
state to the Shift-IR TAP state. Data written to the TDO buffer can be driven serially onto the TDO pin and bits
received serially at the TDI pin can be stored in the TDI buffer for reading by the host. The number of data bits
transferred in and/or out is determined by the value of the counter upon command initiation. If, during the
operation of an instruction register scan command, the TDO buffer becomes empty or the TDI buffer becomes
full, the TAP state is sequenced to Pause-IR (if in free-running-TCK mode) or the TCK output is gated off (if in
gated-TCK mode) until the required buffer service is performed. Upon the countdown of the counter to zero,
the eTBC generates TMS sequences to move the target scan chain to the end state specified in the command
register.
data-register scan commands
The data-register scan commands operate to scan bits to and/or from the concatenation of data registers in a
target scan chain. The eTBC generates a TMS sequence to move the target scan chain from its current TAP
state to the Shift-DR TAP state. Data written to the TDO buffer can be driven serially onto the TDO pin and bits
received serially at the TDI pin can be stored in the TDI buffer for reading by the host. The number of data bits
transferred in and/or out is determined by the value of the counter upon command initiation. If, during the
operation of a data-register scan command, the TDO buffer becomes empty or the TDI buffer becomes full, the
TAP state is sequenced to Pause-DR (if in free-running-TCK mode) or the TCK output is gated off (if in
gated-TCK mode) until the required buffer service is performed. Upon the countdown of the counter to zero,
the eTBC generates TMS sequences to move the target scan chain to the end state specified in the
command register.
other scan-command variations
As noted before, the nature/direction of the data transfer for any scan command can vary, along with the
destination of scan data in the target, as follows:
D For scan commands of the full-duplex (default) class, both TDO buffer and TDI buffer are used to scan data
to and from the target scan chain, respectively.
D For scan commands of the input-only class, only the TDI buffer is used to scan data from the target scan
chain; outgoing TDO data is fixed at a high level throughout the scan operation.
D For scan commands of the output-only class, only the TDO buffer is used to scan data to the target scan
chain; incoming TDI data is simply ignored.
D For scan commands of the recirculate class, only the TDI buffer is used to scan data from the target scan
chain; outgoing TDO data is generated by recirculating the incoming TDI data back into the target
scan chain.
counter
As described above, the value loaded in the eTBC’s 32-bit counter at initiation of a command is used to specify
the number of TCK cycles or scan bits to remain in the command’s working state. As each TCK cycle or scan
bit is processed for a run-test or scan command, respectively, the counter value is decremented. When the
counter value reaches zero, the command leaves its working state to finish in the end state specified in the
command register.
Before a command that uses the counter can be initiated, a full 32-bit value should be loaded by four consecutive
writes to the counter register. As well, the full 32-bit current value of the counter can be observed by four
consecutive reads to the counter register. The counter status (unloaded/loaded) is maintained and observable
in the status register (bit 5, CTRS).
Upon eTBC reset (power-up, hardware-initiated, or software-initiated), the counter is cleared and assumes its
unloaded state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
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