參數(shù)資料
型號(hào)： SN54LVT8980JT
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁(yè)數(shù)： 3/36頁(yè)
文件大?。?/td> 509K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ready output
The ready output (RDY) from the host interface can be used, where the selected microprocessor/microcontroller
supports it, to insert wait or hold states back to the host. If a host-requested access cannot be performed
immediately, RDY goes inactive (low) during that given access. When the condition blocking the access clears,
RDY goes active (high) and the eTBC grants the requested access. Alternatively, where such
hardware-generated hold or wait states are not supported in the selected microprocessor/microcontroller host,
the eTBC status and/or command registers can be polled to determine its readiness to grant a given read or
write access.
Conditions that cause a host access to be blocked (and RDY to become inactive) are limited to the following:
D While the TDI buffer is empty, as indicated in status register (bit 7, TDIS), a requested read to TDI-buffer
register generates RDY inactive; this condition clears, RDY goes active, and the requested access
completes, when the TDI buffer is no longer empty.
D While the TDO buffer is full or is being reset upon initiation of a scan command, as indicated in status register
(bit 6, TDOS), a requested write to TDO-buffer register generates RDY inactive; this condition clears, RDY
goes active, and the requested access completes, when the TDO buffer is no longer full or the TDO-buffer
reset completes, as applicable.
D While a command is in progress, as indicated by a non-zero value in the opcode field (bits 3–0, OPCOD)
of the command register, a requested write to command, configurationA, configurationB, or counter
registers generates RDY inactive. This condition clears, RDY goes active, and the requested access is
complete, when the previously specified command finishes. The sole exception is the writing of a logic 1
into the software reset (bit 7, SWRST) bit of the command register, which is never blocked.
D While a full-duplex scan command is in progress, and the number of retiming-delay bits is other than zero,
the number of writes to TDO-buffer register may not exceed, by more than 5, the number of reads to
TDI-buffer register. A write to TDO-buffer register that does exceed this limit is blocked, and generates RDY
inactive, indefinitely; the TDI-buffer register must be read before another write to TDO-buffer register.
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